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| author | Tamar Christina <tamar.christina@arm.com> | 2017-11-09 11:21:31 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-11-09 11:21:31 +0000 |
| commit | b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb (patch) | |
| tree | 2c4abe3fa1daf67b9c26fb249689cd78b2b7d8df /include | |
| parent | 21b81e67c73368dbbc9f6356ac5a7eb274789a32 (diff) | |
| download | gdb-b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb.zip gdb-b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb.tar.gz gdb-b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb.tar.bz2 | |
Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions.
gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
(aarch64_features): Added SM4 and SHA3.
include * opcode/aarch64.h:
(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.
opcodes * aarch64-tbl.h
(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
(aarch64_feature_sm4, aarch64_feature_sha3): New.
(aarch64_feature_fp_16_v8_2): New.
(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
(V8_4_INSN, CRYPTO_V8_2_INSN): New.
(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index c27ec9c..4e3002f 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2017-11-09 Tamar Christina <tamar.christina@arm.com> + + * opcode/aarch64.h: + (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. + (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. + 2017-11-09 Nick Clifton <nickc@redhat.com> * opcode/aarch64.h (aarch64_feature_set): Change type to unsigned diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a597ebe..2038164 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -39,6 +39,9 @@ typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ #define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ #define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ +#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ +#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ +#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ @@ -77,6 +80,8 @@ typedef uint32_t aarch64_insn; AARCH64_FEATURE_V8_3 \ | AARCH64_FEATURE_RCPC \ | AARCH64_FEATURE_COMPNUM) +#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ + AARCH64_FEATURE_V8_4) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ |