New ARC implementation.

bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.

9 files changed, 1088 insertions, 268 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index e4914ed..5301696 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* dis-asm.h (arc_get_disassembler): Correct declaration.
+
 2015-09-30  Nick Clifton  <nickc@redhat.com>
 
 	Import the following patches from the GCC mainline:
diff --git a/include/dis-asm.h b/include/dis-asm.h
index ebc2604..f82149b 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -319,7 +319,7 @@ extern int print_insn_rl78_g10		(bfd_vma, disassemble_info *);
 extern int print_insn_rl78_g13		(bfd_vma, disassemble_info *);
 extern int print_insn_rl78_g14		(bfd_vma, disassemble_info *);
 
-extern disassembler_ftype arc_get_disassembler (void *);
+extern disassembler_ftype arc_get_disassembler (bfd *);
 extern disassembler_ftype cris_get_disassembler (bfd *);
 extern disassembler_ftype rl78_get_disassembler (bfd *);
 
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 8e6bb44..5e4605d 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,12 @@
+2015-10-07  Cupertino Miranda  <cmiranda@synopsys.com>
+
+	* arc-reloc.def: Macro file with definition of all relocation
+	types.
+	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
+	enum defining the supported relocations.
+	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
+	macro for EM_ARC_COMPACT2.
+
 2015-09-22  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
 	* common.h (DF_1_STUB, DF_1_PIE): Define.
diff --git a/include/elf/arc-reloc.def b/include/elf/arc-reloc.def
new file mode 100644
index 0000000..e2ff871
--- /dev/null
+++ b/include/elf/arc-reloc.def
@@ -0,0 +1,456 @@
+
+ARC_RELOC_HOWTO(ARC_NONE, 0, \
+                2, \
+                32, \
+                replace_none, \
+                bitfield, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_8, 1, \
+                0, \
+                8, \
+                replace_bits8, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_16, 2, \
+                1, \
+                16, \
+                replace_bits16, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_24, 3, \
+                2, \
+                24, \
+                replace_bits24, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_32, 4, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_N8, 8, \
+                0, \
+                8, \
+                replace_bits8, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N16, 9, \
+                1, \
+                16, \
+                replace_bits16, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N24, 10, \
+                2, \
+                24, \
+                replace_bits24, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_N32, 11, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_SDA, 12, \
+                2, \
+                9, \
+                replace_disp9, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF, 13, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S - SECTSTART ) + A ))
+
+ARC_RELOC_HOWTO(ARC_S21H_PCREL, 14, \
+                2, \
+                20, \
+                replace_disp21h, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_S21W_PCREL, 15, \
+                2, \
+                19, \
+                replace_disp21w, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S25H_PCREL, 16, \
+                2, \
+                24, \
+                replace_disp25h, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_S25W_PCREL, 17, \
+                2, \
+                23, \
+                replace_disp25w, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA32, 18, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST, 19, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST1, 20, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST2, 21, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD, 22, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD1, 23, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_LD2, 24, \
+                1, \
+                9, \
+                replace_disp9s, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S13_PCREL, 25, \
+                1, \
+                11, \
+                replace_disp13s, \
+                signed, \
+                ( ( ( S + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_W, 26, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S + A ) & ( ~3 ) ))
+
+ARC_RELOC_HOWTO(ARC_32_ME, 27, \
+                2, \
+                32, \
+                replace_limm, \
+                signed, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_32_ME_S, 105, \
+                2, \
+                32, \
+                replace_limms, \
+                signed, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_N32_ME, 28, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S - A ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME, 29, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( S - SECTSTART ) + A ))
+
+ARC_RELOC_HOWTO(ARC_SDA32_ME, 30, \
+                2, \
+                32, \
+                replace_limm, \
+                signed, \
+                ( ( S + A ) - _SDA_BASE_ ))
+
+ARC_RELOC_HOWTO(ARC_W_ME, 31, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( S + A ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8, 35, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( S + A ) - SECTSTART ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8_1, 36, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 1 ))
+
+ARC_RELOC_HOWTO(AC_SECTOFF_U8_2, 37, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 2 ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9, 38, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( S + A ) - SECTSTART ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9_1, 39, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 1 ))
+
+ARC_RELOC_HOWTO(AC_SECTFOFF_S9_2, 40, \
+                2, \
+                9, \
+                replace_disp9ls, \
+                bitfield, \
+                ( ( ( S + A ) - SECTSTART ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME_1, 41, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_ME_2, 42, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_1, 43, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_SECTOFF_2, 44, \
+                2, \
+                32, \
+                replace_word32, \
+                bitfield, \
+                ( ( ( S - SECTSTART ) + A ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_SDA16_ST2, 48, \
+                1, \
+                9, \
+                replace_disp9s1, \
+                signed, \
+                ( ( ( S + A ) - _SDA_BASE_ ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_PC32, 50, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_GOT32, 59, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                ( G + A ))
+
+ARC_RELOC_HOWTO(ARC_GOTPC32, 51, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( ( GOT + G ) + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_PLT32, 52, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( L + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_COPY, 53, \
+                2, \
+                0, \
+                replace_none, \
+                signed, \
+                none)
+
+ARC_RELOC_HOWTO(ARC_GLOB_DAT, 54, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                S)
+
+ARC_RELOC_HOWTO(ARC_JMP_SLOT, 55, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                S)
+
+ARC_RELOC_HOWTO(ARC_RELATIVE, 56, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( B + A ))
+
+ARC_RELOC_HOWTO(ARC_GOTOFF, 57, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( S + A ) - GOT ))
+
+ARC_RELOC_HOWTO(ARC_GOTPC, 58, \
+                2, \
+                32, \
+                replace_word32, \
+                signed, \
+                ( ( GOT + A ) - P ))
+
+ARC_RELOC_HOWTO(ARC_S21W_PCREL_PLT, 60, \
+                2, \
+                19, \
+                replace_disp21w, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S25H_PCREL_PLT, 61, \
+                2, \
+                24, \
+                replace_disp25h, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 1 ))
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPMOD, 66, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPOFF, 67, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_TPOFF, 68, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_GOT, 69, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_LD, 70, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_GD_CALL, 71, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_IE_GOT, 72, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_DTPOFF_S9, 73, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_LE_S9, 74, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_TLS_LE_32, 75, \
+                2, \
+                32, \
+                replace_word32, \
+                dont, \
+                0)
+
+ARC_RELOC_HOWTO(ARC_S25W_PCREL_PLT, 76, \
+                2, \
+                23, \
+                replace_disp25w, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 2 ))
+
+ARC_RELOC_HOWTO(ARC_S21H_PCREL_PLT, 77, \
+                2, \
+                20, \
+                replace_disp21h, \
+                signed, \
+                ( ( ( L + A ) - P ) >> 1 ))
+
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 62398e1..707aeb4 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -28,25 +28,41 @@
 
 /* Relocations.  */
 
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+  RELOC_NUMBER(R_##TYPE, VALUE)
+
 START_RELOC_NUMBERS (elf_arc_reloc_type)
-  RELOC_NUMBER (R_ARC_NONE, 0)
-  RELOC_NUMBER (R_ARC_32, 1)
-  RELOC_NUMBER (R_ARC_B26, 2)
-  RELOC_NUMBER (R_ARC_B22_PCREL, 3)
+#include "arc-reloc.def"
 END_RELOC_NUMBERS (R_ARC_max)
 
+#undef ARC_RELOC_HOWTO
+
 /* Processor specific flags for the ELF header e_flags field.  */
 
 /* Four bit ARC machine type field.  */
+#define EF_ARC_MACH_MSK	 0x000000ff
+#define EF_ARC_OSABI_MSK 0x00000f00
+#define EF_ARC_ALL_MSK	 (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
+
+/* Four bit ARC machine type field.  */
 
 #define EF_ARC_MACH 0x0000000f
 
 /* Various CPU types.  */
+#define E_ARC_MACH_ARC600	0x00000002
+#define E_ARC_MACH_ARC601	0x00000004
+#define E_ARC_MACH_ARC700	0x00000003
 
-#define E_ARC_MACH_ARC5 0
-#define E_ARC_MACH_ARC6 1	
-#define E_ARC_MACH_ARC7 2
-#define E_ARC_MACH_ARC8 3
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARC_CPU_GENERIC      0x00000000
+#define EF_ARC_CPU_ARCV2EM      0x00000005
+#define EF_ARC_CPU_ARCV2HS      0x00000006
+
+/* ARC Linux specific ABIs.  */
+#define E_ARC_OSABI_ORIG	0x00000000   /* MUST be 0 for back-compat.  */
+#define E_ARC_OSABI_V2		0x00000200
+#define E_ARC_OSABI_V3		0x00000300
+#define E_ARC_OSABI_CURRENT	E_ARC_OSABI_V3
 
 /* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.  */
 
diff --git a/include/elf/common.h b/include/elf/common.h
index fbf1f3c..bb15b7d 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -194,7 +194,7 @@
 #define EM_MN10200	 90	/* Matsushita MN10200 */
 #define EM_PJ		 91	/* picoJava */
 #define EM_OR1K		 92	/* OpenRISC 1000 32-bit embedded processor */
-#define EM_ARC_A5	 93	/* ARC Cores Tangent-A5 */
+#define EM_ARC_COMPACT	 93	/* ARC International ARCompact processor */
 #define EM_XTENSA	 94	/* Tensilica Xtensa Architecture */
 #define EM_VIDEOCORE	 95	/* Alphamosaic VideoCore processor */
 #define EM_TMM_GPP	 96	/* Thompson Multimedia General Purpose Processor */
@@ -295,6 +295,7 @@
 #define EM_MICROBLAZE	189	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
 #define EM_CUDA		190	/* NVIDIA CUDA architecture */
 #define EM_TILEGX	191	/* Tilera TILE-Gx multicore architecture family */
+#define EM_ARC_COMPACT2 195	/* Synopsys ARCompact V2 */
 #define EM_RL78		197	/* Renesas RL78 family.  */
 #define EM_78K0R	199	/* Renesas 78K0R.  */
 #define EM_INTEL205	205	/* Reserved by Intel */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a7e9895c..63fe454 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2015-10-07  Claudiu Zissulescu  <claziss@synopsys.com>
+            Cupertino Miranda  <cmiranda@synopsys.com>
+
+        * arc-func.h: New file.
+        * arc.h: Likewise.
+
 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 
 	* aarch64.h (aarch64_zero_register_p): Move the declaration
diff --git a/include/opcode/arc-func.h b/include/opcode/arc-func.h
new file mode 100644
index 0000000..faffcb5
--- /dev/null
+++ b/include/opcode/arc-func.h
@@ -0,0 +1,236 @@
+/* Replace functions for the ARC relocs.
+   Copyright 2015
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* mask  = 00000000000000000000000000000000.  */
+#ifndef REPLACE_none
+#define REPLACE_none
+ATTRIBUTE_UNUSED static unsigned
+replace_none (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+
+  return insn;
+}
+
+#endif /* REPLACE_none */
+
+/* mask  = 11111111.  */
+#ifndef REPLACE_bits8
+#define REPLACE_bits8
+ATTRIBUTE_UNUSED static unsigned
+replace_bits8 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x00ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits8 */
+
+/* mask  = 1111111111111111.  */
+#ifndef REPLACE_bits16
+#define REPLACE_bits16
+ATTRIBUTE_UNUSED static unsigned
+replace_bits16 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits16 */
+
+/* mask  = 111111111111111111111111.  */
+#ifndef REPLACE_bits24
+#define REPLACE_bits24
+ATTRIBUTE_UNUSED static unsigned
+replace_bits24 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_bits24 */
+
+/* mask  = 11111111111111111111111111111111.  */
+#ifndef REPLACE_word32
+#define REPLACE_word32
+ATTRIBUTE_UNUSED static unsigned
+replace_word32 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_word32 */
+
+/* mask  = 0000000000000000000000000000000011111111111111111111111111111111.  */
+#ifndef REPLACE_limm
+#define REPLACE_limm
+ATTRIBUTE_UNUSED static unsigned
+replace_limm (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_limm */
+
+/* mask  = 000000000000000011111111111111111111111111111111.  */
+#ifndef REPLACE_limms
+#define REPLACE_limms
+ATTRIBUTE_UNUSED static unsigned
+replace_limms (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0xffffffff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_limms */
+
+/* mask  = 00000111111111102222222222000000.  */
+#ifndef REPLACE_disp21h
+#define REPLACE_disp21h
+ATTRIBUTE_UNUSED static unsigned
+replace_disp21h (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x03ff) << 17;
+  insn |= ((value >> 10) & 0x03ff) << 6;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp21h */
+
+/* mask  = 00000111111111002222222222000000.  */
+#ifndef REPLACE_disp21w
+#define REPLACE_disp21w
+ATTRIBUTE_UNUSED static unsigned
+replace_disp21w (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 18;
+  insn |= ((value >> 9) & 0x03ff) << 6;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp21w */
+
+/* mask  = 00000111111111102222222222003333.  */
+#ifndef REPLACE_disp25h
+#define REPLACE_disp25h
+ATTRIBUTE_UNUSED static unsigned
+replace_disp25h (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x03ff) << 17;
+  insn |= ((value >> 10) & 0x03ff) << 6;
+  insn |= ((value >> 20) & 0x000f) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp25h */
+
+/* mask  = 00000111111111002222222222003333.  */
+#ifndef REPLACE_disp25w
+#define REPLACE_disp25w
+ATTRIBUTE_UNUSED static unsigned
+replace_disp25w (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 18;
+  insn |= ((value >> 9) & 0x03ff) << 6;
+  insn |= ((value >> 19) & 0x000f) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp25w */
+
+/* mask  = 00000000000000000000000111111111.  */
+#ifndef REPLACE_disp9
+#define REPLACE_disp9
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9 */
+
+/* mask  = 00000000111111112000000000000000.  */
+#ifndef REPLACE_disp9ls
+#define REPLACE_disp9ls
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9ls (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x00ff) << 16;
+  insn |= ((value >> 8) & 0x0001) << 15;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9ls */
+
+/* mask  = 0000000111111111.  */
+#ifndef REPLACE_disp9s
+#define REPLACE_disp9s
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x01ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9s */
+
+/* mask  = 0000011111111111.  */
+#ifndef REPLACE_disp13s
+#define REPLACE_disp13s
+ATTRIBUTE_UNUSED static unsigned
+replace_disp13s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x07ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp13s */
+
+/* mask  = 0000022222200111.  */
+#ifndef REPLACE_disp9s1
+#define REPLACE_disp9s1
+ATTRIBUTE_UNUSED static unsigned
+replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+  insn |= ((value >> 0) & 0x0007) << 0;
+  insn |= ((value >> 3) & 0x003f) << 5;
+
+  return insn;
+}
+
+#endif /* REPLACE_disp9s1 */
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 907e4fb..3dbc541 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -1,6 +1,7 @@
 /* Opcode table for the ARC.
-   Copyright (C) 1994-2015 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
+   Copyright 1994-2015 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
    the GNU Binutils.
@@ -12,7 +13,7 @@
 
    GAS/GDB is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
@@ -20,302 +21,393 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-/* List of the various cpu types.
-   The tables currently use bit masks to say whether the instruction or
-   whatever is supported by a particular cpu.  This lets us have one entry
-   apply to several cpus.
+#ifndef OPCODE_ARC_H
+#define OPCODE_ARC_H
+
+#define MAX_INSN_ARGS	     6
+#define MAX_INSN_FLGS	     3
+
+/* Instruction Class.  */
+typedef enum
+  {
+    ARITH,
+    AUXREG,
+    BRANCH,
+    CONTROL,
+    DSP,
+    FLOAT,
+    INVALID,
+    JUMP,
+    KERNEL,
+    LOGICAL,
+    MEMORY,
+  } insn_class_t;
+
+/* Instruction Subclass.  */
+typedef enum
+  {
+    NONE,
+    CVT,
+    BTSCN,
+    CD1,
+    CD2,
+    DIV,
+    DP,
+    MPY1E,
+    MPY6E,
+    MPY7E,
+    MPY8E,
+    MPY9E,
+    SHFT1,
+    SHFT2,
+    SWAP,
+    SP
+  } insn_subclass_t;
+
+/* Flags class.  */
+typedef enum
+  {
+    FNONE,
+    CND,  /* Conditional flags.  */
+    WBM,  /* Write-back modes.  */
+    FLG,  /* F Flag.  */
+    SBP,  /* Static branch prediction.  */
+    DLY,  /* Delay slot.  */
+    DIF,  /* Bypass caches.  */
+    SGX,  /* Sign extend modes.  */
+    SZM   /* Data size modes.  */
+  } flag_class_t;
+
+/* The opcode table is an array of struct arc_opcode.  */
+struct arc_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned mask;
+
+  /* One bit flags for the opcode.  These are primarily used to
+     indicate specific processors and environments support the
+     instructions.  The defined values are listed below.  */
+  unsigned cpu;
+
+  /* The instruction class.  This is used by gdb.  */
+  insn_class_t class;
+
+  /* The instruction subclass.  */
+  insn_subclass_t subclass;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[MAX_INSN_ARGS + 1];
+
+  /* An array of flag codes.  Each code is an index into the flag
+     table.  They appear in the order which the flags must appear in
+     assembly code, and are terminated by a zero.  */
+  unsigned char flags[MAX_INSN_FLGS + 1];
+};
 
-   The `base' cpu must be 0. The cpu type is treated independently of
-   endianness. The complete `mach' number includes endianness.
-   These values are internal to opcodes/bfd/binutils/gas.  */
-#define ARC_MACH_5 0
-#define ARC_MACH_6 1
-#define ARC_MACH_7 2
-#define ARC_MACH_8 4
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct arc_opcode arc_opcodes[];
+extern const unsigned arc_num_opcodes;
+
+/* CPU Availability.  */
+#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
+#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
+#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
+#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
+
+/* CPU extensions.  */
+#define ARC_EA       0x0001
+#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
+#define ARC_LLOCK    0x0002
+#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
+#define ARC_MPY      0x0004
+#define ARC_MULT     0x0004
+
+/* Floating point support.  */
+#define ARC_DPFP     0x0010
+#define ARC_SPFP     0x0020
+#define ARC_FPU      0x0030
+
+/* NORM & SWAP.  */
+#define ARC_SWAP     0x0100
+#define ARC_NORM     0x0200
+#define ARC_BSCAN    0x0200
+
+/* A7 specific.  */
+#define ARC_UIX      0x1000
+#define ARC_TSTAMP   0x1000
+
+/* A6 specific.  */
+#define ARC_VBFDW    0x1000
+#define ARC_BARREL   0x1000
+#define ARC_DSPA     0x1000
+
+/* EM specific.  */
+#define ARC_SHIFT    0x1000
+
+/* V2 specific.  */
+#define ARC_INTR     0x1000
+#define ARC_DIV      0x1000
+
+/* V1 specific.  */
+#define ARC_XMAC     0x1000
+#define ARC_CRC      0x1000
+
+/* Base architecture -- all cpus.  */
+#define ARC_OPCODE_BASE				\
+  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700	\
+   | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+
+/* A macro to check for short instructions.  */
+#define ARC_SHORT(mask)				\
+  (((mask) & 0xFFFF0000) ? 0 : 1)
+
+/* The operands table is an array of struct arc_operand.  */
+struct arc_operand
+{
+  /* The number of bits in the operand.  */
+  unsigned int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  unsigned int shift;
+
+  /* The default relocation type for this operand.  */
+  signed int default_reloc;
+
+  /* One bit syntax flags.  */
+  unsigned int flags;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.	 It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).	 If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
+	     && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.	 It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     TRUE if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  int (*extract) (unsigned instruction, bfd_boolean *invalid);
+};
 
-/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
-#define ARC_MACH_BIG 16
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the arc_opcodes table.  */
+extern const struct arc_operand arc_operands[];
+extern const unsigned arc_num_operands;
+extern const unsigned arc_Toperand;
+extern const unsigned arc_NToperand;
 
-/* Mask of number of bits necessary to record cpu type.  */
-#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
+/* Values defined for the flags field of a struct arc_operand.  */
 
-/* Mask of number of bits necessary to record cpu type + endianness.  */
-#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics, for which two operands fields
+   are identical.  The assembler should call the insert function with
+   any op value.  The disassembler should call the extract function,
+   ignore the return value, and check the value placed in the invalid
+   argument.  */
+#define ARC_OPERAND_FAKE	0x0001
 
-/* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+/* This operand names an integer register.  */
+#define ARC_OPERAND_IR		0x0002
 
-typedef unsigned int arc_insn;
+/* This operand takes signed values.  */
+#define ARC_OPERAND_SIGNED	0x0004
 
-struct arc_opcode {
-  char *syntax;              /* syntax of insn  */
-  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
-  int flags;                 /* various flag bits  */
+/* This operand takes unsigned values.  This exists primarily so that
+   a flags value of 0 can be treated as end-of-arguments.  */
+#define ARC_OPERAND_UNSIGNED	0x0008
 
-/* Values for `flags'.  */
+/* This operand takes long immediate values.  */
+#define ARC_OPERAND_LIMM	0x0010
 
-/* Return CPU number, given flag bits.  */
-#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* This operand is identical like the previous one.  */
+#define ARC_OPERAND_DUPLICATE   0x0020
 
-/* Return MACH number, given flag bits.  */
-#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+/* This operand is PC relative.  Used for internal relocs.  */
+#define ARC_OPERAND_PCREL       0x0040
 
-/* First opcode flag bit available after machine mask.  */
-#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
+/* This operand is truncated.  The truncation is done accordingly to
+   operand alignment attribute.  */
+#define ARC_OPERAND_TRUNCATE    0x0080
 
-/* This insn is a conditional branch.  */
-#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
-#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
-#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
-#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
-#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
-#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
-#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
+/* This operand is 16bit aligned.  */
+#define ARC_OPERAND_ALIGNED16   0x0100
 
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
+/* This operand is 32bit aligned.  */
+#define ARC_OPERAND_ALIGNED32   0x0200
 
-/* These values are used to optimize assembly and disassembly.  Each insn
-   is on a list of related insns (same first letter for assembly, same
-   insn code for disassembly).  */
+/* This operand can be ignored by matching process if it is not
+   present.  */
+#define ARC_OPERAND_IGNORE      0x0400
 
-  struct arc_opcode *next_asm;	/* Next instr to try during assembly.  */
-  struct arc_opcode *next_dis;	/* Next instr to try during disassembly.  */
+/* Don't check the range when matching.	 */
+#define ARC_OPERAND_NCHK	0x0800
 
-/* Macros to create the hash values for the lists.  */
-#define ARC_HASH_OPCODE(string) \
-  ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
-#define ARC_HASH_ICODE(insn) \
-  ((unsigned int) (insn) >> 27)
+/* Mark the braket possition.  */
+#define ARC_OPERAND_BRAKET      0x1000
 
- /* Macros to access `next_asm', `next_dis' so users needn't care about the
-    underlying mechanism.  */
-#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
-#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
-};
+/* Mask for selecting the type for typecheck purposes.  */
+#define ARC_OPERAND_TYPECHECK_MASK		\
+  (ARC_OPERAND_IR |				\
+   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
+   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 
-/* this is an "insert at front" linked list per Metaware spec
-   that new definitions override older ones.  */
-extern struct arc_opcode *arc_ext_opcodes;
+/* The flags structure.  */
+struct arc_flag_operand
+{
+  /* The flag name.  */
+  const char *name;
 
-struct arc_operand_value {
-  char *name;          /* eg: "eq"  */
-  short value;         /* eg: 1  */
-  unsigned char type;  /* index into `arc_operands'  */
-  unsigned char flags; /* various flag bits  */
+  /* The flag code.  */
+  unsigned code;
 
-/* Values for `flags'.  */
+  /* The number of bits in the operand.  */
+  unsigned int bits;
 
-/* Return CPU number, given flag bits.  */
-#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
-/* Return MACH number, given flag bits.  */
-#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
-};
+  /* How far the operand is left shifted in the instruction.  */
+  unsigned int shift;
 
-struct arc_ext_operand_value {
-  struct arc_ext_operand_value *next;
-  struct arc_operand_value operand;
+  /* Available for disassembler.  */
+  unsigned char favail;
 };
 
-extern struct arc_ext_operand_value *arc_ext_operands;
+/* The flag operands table.  */
+extern const struct arc_flag_operand arc_flag_operands[];
+extern const unsigned arc_num_flag_operands;
 
-struct arc_operand {
-/* One of the insn format chars.  */
-  unsigned char fmt;
+/* The flag's class structure.  */
+struct arc_flag_class
+{
+  /* Flag class.  */
+  flag_class_t class;
 
-/* The number of bits in the operand (may be unused for a modifier).  */
-  unsigned char bits;
+  /* List of valid flags (codes).  */
+  unsigned flags[256];
+};
 
-/* How far the operand is left shifted in the instruction, or
-   the modifier's flag bit (may be unused for a modifier.  */
-  unsigned char shift;
+extern const struct arc_flag_class arc_flag_classes[];
 
-/* Various flag bits.  */
-  int flags;
+/* Structure for special cases.  */
+struct arc_flag_special
+{
+  /* Name of special case instruction.  */
+  const char *name;
 
-/* Values for `flags'.  */
+  /* List of flags applicable for special case instruction.  */
+  unsigned flags[32];
+};
 
-/* This operand is a suffix to the opcode.  */
-#define ARC_OPERAND_SUFFIX 1
+extern const struct arc_flag_special arc_flag_special_cases[];
+extern const unsigned arc_num_flag_special;
+
+/* Relocation equivalence structure.  */
+struct arc_reloc_equiv_tab
+{
+  const char * name;	   /* String to lookup.  */
+  const char * mnemonic;   /* Extra matching condition.  */
+  unsigned     flagcode;   /* Extra matching condition.  */
+  signed int   oldreloc;   /* Old relocation.  */
+  signed int   newreloc;   /* New relocation.  */
+};
 
-/* This operand is a relative branch displacement.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_RELATIVE_BRANCH 2
+extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
+extern const unsigned arc_num_equiv_tab;
 
-/* This operand is an absolute branch address.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_ABSOLUTE_BRANCH 4
+/* Structure for operand operations for pseudo/alias instructions.  */
+struct arc_operand_operation
+{
+  /* The index for operand from operand array.  */
+  unsigned operand_idx;
 
-/* This operand is an address.  The disassembler
-   prints these symbolically if possible.  */
-#define ARC_OPERAND_ADDRESS 8
+  /* Defines if it needs the operand inserted by the assembler or
+     whether this operand comes from the pseudo instruction's
+     operands.  */
+  unsigned char needs_insert;
 
-/* This operand is a long immediate value.  */
-#define ARC_OPERAND_LIMM 0x10
+  /* Count we have to add to the operand.  Use negative number to
+     subtract from the operand.  Also use this number to add to 0 if
+     the operand needs to be inserted (i.e. needs_insert == 1).  */
+  int count;
 
-/* This operand takes signed values.  */
-#define ARC_OPERAND_SIGNED 0x20
-
-/* This operand takes signed values, but also accepts a full positive
-   range of values.  That is, if bits is 16, it takes any value from
-   -0x8000 to 0xffff.  */
-#define ARC_OPERAND_SIGNOPT 0x40
-
-/* This operand should be regarded as a negative number for the
-   purposes of overflow checking (i.e., the normal most negative
-   number is disallowed and one more than the normal most positive
-   number is allowed).  This flag will only be set for a signed
-   operand.  */
-#define ARC_OPERAND_NEGATIVE 0x80
-
-/* This operand doesn't really exist.  The program uses these operands
-   in special ways.  */
-#define ARC_OPERAND_FAKE 0x100
-
-/* separate flags operand for j and jl instructions  */
-#define ARC_OPERAND_JUMPFLAGS 0x200
-
-/* allow warnings and errors to be issued after call to insert_xxxxxx  */
-#define ARC_OPERAND_WARN  0x400
-#define ARC_OPERAND_ERROR 0x800
-
-/* this is a load operand */
-#define ARC_OPERAND_LOAD  0x8000
-
-/* this is a store operand */
-#define ARC_OPERAND_STORE 0x10000
-
-/* Modifier values.  */
-/* A dot is required before a suffix.  Eg: .le  */
-#define ARC_MOD_DOT 0x1000
-
-/* A normal register is allowed (not used, but here for completeness).  */
-#define ARC_MOD_REG 0x2000
-
-/* An auxiliary register name is expected.  */
-#define ARC_MOD_AUXREG 0x4000
-
-/* Sum of all ARC_MOD_XXX bits.  */
-#define ARC_MOD_BITS 0x7000
-
-/* Non-zero if the operand type is really a modifier.  */
-#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
-
-/* enforce read/write only register restrictions  */
-#define ARC_REGISTER_READONLY    0x01
-#define ARC_REGISTER_WRITEONLY   0x02
-#define ARC_REGISTER_NOSHORT_CUT 0x04
-
-/* Insertion function.  This is used by the assembler.  To insert an
-   operand value into an instruction, check this field.
-
-   If it is NULL, execute
-   i |= (p & ((1 << o->bits) - 1)) << o->shift;
-   (I is the instruction which we are filling in, O is a pointer to
-   this structure, and OP is the opcode value; this assumes twos
-   complement arithmetic).
-   
-   If this field is not NULL, then simply call it with the
-   instruction and the operand value.  It will return the new value
-   of the instruction.  If the ERRMSG argument is not NULL, then if
-   the operand value is illegal, *ERRMSG will be set to a warning
-   string (the operand will be inserted in any case).  If the
-   operand value is legal, *ERRMSG will be unchanged.
-
-   REG is non-NULL when inserting a register value.  */
-
-  arc_insn (*insert)
-    (arc_insn insn, const struct arc_operand *operand, int mods,
-     const struct arc_operand_value *reg, long value, const char **errmsg);
-
-/* Extraction function.  This is used by the disassembler.  To
-   extract this operand type from an instruction, check this field.
-   
-   If it is NULL, compute
-     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
-     if ((o->flags & ARC_OPERAND_SIGNED) != 0
-          && (op & (1 << (o->bits - 1))) != 0)
-       op -= 1 << o->bits;
-   (I is the instruction, O is a pointer to this structure, and OP
-   is the result; this assumes twos complement arithmetic).
-   
-   If this field is not NULL, then simply call it with the
-   instruction value.  It will return the value of the operand.  If
-   the INVALID argument is not NULL, *INVALID will be set to
-   non-zero if this operand type can not actually be extracted from
-   this operand (i.e., the instruction does not match).  If the
-   operand is valid, *INVALID will not be changed.
-
-   INSN is a pointer to an array of two `arc_insn's.  The first element is
-   the insn, the second is the limm if present.
-
-   Operands that have a printable form like registers and suffixes have
-   their struct arc_operand_value pointer stored in OPVAL.  */
-
-  long (*extract)
-    (arc_insn *insn, const struct arc_operand *operand, int mods,
-     const struct arc_operand_value **opval, int *invalid);
+  /* Index of the operand to swap with.  To be done AFTER applying
+     inc_count.  */
+  unsigned swap_operand_idx;
 };
 
-/* Bits that say what version of cpu we have. These should be passed to
-   arc_init_opcode_tables. At present, all there is is the cpu type.  */
+/* Structure for pseudo/alias instructions.  */
+struct arc_pseudo_insn
+{
+  /* Mnemonic for pseudo/alias insn.  */
+  const char *mnemonic_p;
 
-/* CPU number, given value passed to `arc_init_opcode_tables'.  */
-#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
-/* MACH number, given value passed to `arc_init_opcode_tables'.  */
-#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
+  /* Mnemonic for real instruction.  */
+  const char *mnemonic_r;
 
-/* Special register values:  */
-#define ARC_REG_SHIMM_UPDATE 61
-#define ARC_REG_SHIMM 63
-#define ARC_REG_LIMM 62
+  /* Flag that will have to be added (if any).  */
+  const char *flag_r;
 
-/* Non-zero if REG is a constant marker.  */
-#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
+  /* Amount of operands.  */
+  unsigned operand_cnt;
 
-/* Positions and masks of various fields:  */
-#define ARC_SHIFT_REGA 21
-#define ARC_SHIFT_REGB 15
-#define ARC_SHIFT_REGC 9
-#define ARC_MASK_REG 63
+  /* Array of operand operations.  */
+  struct arc_operand_operation operand[6];
+};
 
-/* Delay slot types.  */
-#define ARC_DELAY_NONE 0   /* no delay slot */
-#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
-#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
+extern const struct arc_pseudo_insn arc_pseudo_insns[];
+extern const unsigned arc_num_pseudo_insn;
 
-/* Non-zero if X will fit in a signed 9 bit field.  */
-#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
+/* Structure for AUXILIARY registers.  */
+struct arc_aux_reg
+{
+  /* Register address.  */
+  int address;
 
-extern const struct arc_operand arc_operands[];
-extern const int arc_operand_count;
-extern struct arc_opcode arc_opcodes[];
-extern const int arc_opcodes_count;
-extern const struct arc_operand_value arc_suffixes[];
-extern const int arc_suffixes_count;
-extern const struct arc_operand_value arc_reg_names[];
-extern const int arc_reg_names_count;
-extern unsigned char arc_operand_map[];
-
-/* Utility fns in arc-opc.c.  */
-int arc_get_opcode_mach (int, int);
-
-/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
-void arc_opcode_init_tables (int);
-void arc_opcode_init_insert (void);
-void arc_opcode_init_extract (void);
-const struct arc_opcode *arc_opcode_lookup_asm (const char *);
-const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
-int arc_opcode_limm_p (long *);
-const struct arc_operand_value *arc_opcode_lookup_suffix
-  (const struct arc_operand *type, int value);
-int arc_opcode_supported (const struct arc_opcode *);
-int arc_opval_supported (const struct arc_operand_value *);
-int arc_limm_fixup_adjust (arc_insn);
-int arc_insn_is_j (arc_insn);
-int arc_insn_not_jl (arc_insn);
-int arc_operand_type (int);
-struct arc_operand_value *get_ext_suffix (char *);
-int arc_get_noshortcut_flag (void);
+ /* Register name.  */
+  const char *name;
+
+  /* Size of the string.  */
+  size_t length;
+};
+
+extern const struct arc_aux_reg arc_aux_regs[];
+extern const unsigned arc_num_aux_regs;
+
+#endif /* OPCODE_ARC_H */