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| author | Andrew Jenner <andrew@codesourcery.com> | 2016-08-01 09:42:31 -0700 |
|---|---|---|
| committer | Andrew Jenner <andrew@codesourcery.com> | 2016-08-01 09:42:31 -0700 |
| commit | dfdaec14b0db059497b47b515d753b6383772b6b (patch) | |
| tree | 72366f1f5328fe6631d4727d2b82daa9e800c0df /include | |
| parent | 751b375e01e7e85aeccdd965578cb2040836593d (diff) | |
| download | gdb-dfdaec14b0db059497b47b515d753b6383772b6b.zip gdb-dfdaec14b0db059497b47b515d753b6383772b6b.tar.gz gdb-dfdaec14b0db059497b47b515d753b6383772b6b.tar.bz2 | |
Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.
bfd/
* elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
(ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
(ppc_elf_vle_split16): Clear field before inserting.
opcodes/
* ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
'e_cmplwi' to 'e_cmpli' instead.
(OPVUPRT, OPVUPRT_MASK): Define.
(powerpc_opcodes): Add E200Z4 insns.
(vle_opcodes): Add context save/restore insns.
include/
* opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index a87c9b6..673f757 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2016-08-01 Andrew Jenner <andrew@codesourcery.com> + + * opcode/ppc.h (PPC_OPCODE_E200Z4): New define. + 2016-07-27 Graham Markall <graham.markall@embecosm.com> * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 628a7a1..d9f973d 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -214,6 +214,9 @@ extern const int vle_num_opcodes; /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */ #define PPC_OPCODE_VSX3 0x40000000000ull + /* Opcode is supported by e200z4. */ +#define PPC_OPCODE_E200Z4 0x80000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |