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authorCatherine Moore <clm@codesourcery.com>2013-11-11 08:03:47 -0800
committerCatherine Moore <clm@codesourcery.com>2013-11-11 08:03:47 -0800
commit67dc82bc511e35ef134952014b4deb2fdcf10676 (patch)
tree42bfe2316900f645cba2e3bab5ed60b2f8590e03 /include
parent2df4d1d5c4393fd06c2bffe75499e70a8d8ac8a8 (diff)
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2013-11-11 Catherine Moore <clm@codesourcery.com>
gas/ * config/mips/tc-mips.c (convert_reg_type): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (reg_needs_delay): Likewise. (insns_between): Likewise. include/ * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... (INSN_LOAD_MEMORY): ...this. opcodes/ * mips-dis.c (print_insn_mips): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (print_insn_micromips): Likewise. * mips-opc.c (LDD): Remove. (CLD): Include INSN_LOAD_MEMORY. (LM): New. (mips_builtin_opcodes): Use LM instead of LDD. Add LM to load instructions.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/mips.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index cb16d2a..c9dc52b 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -973,8 +973,8 @@ struct mips_opcode
#define INSN_TLB 0x00000200
/* Reads coprocessor register other than floating point register. */
#define INSN_COP 0x00000400
-/* Instruction loads value from memory, requiring delay. */
-#define INSN_LOAD_MEMORY_DELAY 0x00000800
+/* Instruction loads value from memory. */
+#define INSN_LOAD_MEMORY 0x00000800
/* Instruction loads value from coprocessor, requiring delay. */
#define INSN_LOAD_COPROC_DELAY 0x00001000
/* Instruction has unconditional branch delay slot. */