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authorJoseph Myers <joseph@codesourcery.com>2009-02-03 18:16:04 +0000
committerJoseph Myers <joseph@codesourcery.com>2009-02-03 18:16:04 +0000
commit52b6b6b972d426d44aa9ada61cf7f052d350a3cc (patch)
treec4dbf41fdece504534dfb283a5f7a7036e4c4af7 /include
parenta53fddce83af312fd3aa023c66b007b9e3937805 (diff)
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2009-02-03 Sandip Matte <sandip@rmicorp.com> * aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr. * archures.c (bfd_mach_mips_xlr): Define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_xlr): Define. (arch_info_struct): Add XLR entry. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR. (mips_set_isa_flags): Handle bfd_mach_mips_xlr (mips_mach_extensions): Add XLR entry. binutils: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR. gas: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT and M_MSGWAIT_T. (mips_cpu_info_table): Add XLR entry. * doc/c-mips.texi (-march): Document xlr. gas/testsuite: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * gas/mips/mips.exp (xlr): New architecture. (xlr-ext): Run test. * gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New. include/elf: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (E_MIPS_MACH_XLR): Define. include/opcode: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (INSN_XLR): Define. (INSN_CHIP_MASK): Update. (CPU_XLR): Define. (OPCODE_IS_MEMBER): Update. (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. opcodes: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define. (mips_arch_choices): Add XLR entry. * mips-opc.c (XLR): Define. (mips_builtin_opcodes): Add XLR instructions.
Diffstat (limited to 'include')
-rw-r--r--include/elf/ChangeLog4
-rw-r--r--include/elf/mips.h1
-rw-r--r--include/opcode/ChangeLog8
-rw-r--r--include/opcode/mips.h11
4 files changed, 23 insertions, 1 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 0a4f94c..ab3bb8f 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2009-02-03 Sandip Matte <sandip@rmicorp.com>
+
+ * mips.h (E_MIPS_MACH_XLR): Define.
+
2009-02-03 Maxim Kuvyrkov <maxim@codesourcery.com>
* m68k.h: Map TLS relocations to numbers.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 4ec7816..609da56 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -214,6 +214,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
#define E_MIPS_MACH_OCTEON 0x008b0000
+#define E_MIPS_MACH_XLR 0x008c0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 0ebadf7..e256e6e 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2009-02-03 Sandip Matte <sandip@rmicorp.com>
+
+ * mips.h (INSN_XLR): Define.
+ (INSN_CHIP_MASK): Update.
+ (CPU_XLR): Define.
+ (OPCODE_IS_MEMBER): Update.
+ (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
+
2009-01-28 Doug Evans <dje@google.com>
* opcode/i386.h: Add multiple inclusion protection.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e7cfdb9..a4017a1 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -543,7 +543,7 @@ static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0800
+#define INSN_CHIP_MASK 0xc3ff0820
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
@@ -592,6 +592,8 @@ static const unsigned int mips_isa_table[] =
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* RMI Xlr instruction */
+#define INSN_XLR 0x00000020
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -644,6 +646,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
+#define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -677,6 +680,7 @@ static const unsigned int mips_isa_table[] =
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
+ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
@@ -809,6 +813,11 @@ enum
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
+ M_MSGSND,
+ M_MSGLD,
+ M_MSGLD_T,
+ M_MSGWAIT,
+ M_MSGWAIT_T,
M_MOVE,
M_MUL,
M_MUL_I,