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authorAlan Modra <amodra@gmail.com>2016-12-21 19:13:52 +1030
committerAlan Modra <amodra@gmail.com>2016-12-21 19:18:46 +1030
commit4e25adb3956f880efc28bfebabe79be7338b413f (patch)
tree9e8b41dbf37bac5ab3c6c78abdd26ff6c59019fc /include
parent9962fe293d16e1e1e4d05154e751fc7576226954 (diff)
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Remove high bit set characters
gas/ * doc/c-lm32.texi: Fix chars with high bit set. * testsuite/gas/bfin/vector2.s: Likewise. gold/ * arm.cc: Fix comment chars with high bit set. include/ * coff/pe.h: Fix comment chars with high bit set. * opcode/xgate.h: Likewise. ld/ * testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog5
-rw-r--r--include/coff/pe.h2
-rw-r--r--include/opcode/xgate.h16
3 files changed, 14 insertions, 9 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index aeb3797..2f76430 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-21 Alan Modra <amodra@gmail.com>
+
+ * coff/pe.h: Fix comment chars with high bit set.
+ * opcode/xgate.h: Likewise.
+
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
diff --git a/include/coff/pe.h b/include/coff/pe.h
index 85ad518..fd96fd4 100644
--- a/include/coff/pe.h
+++ b/include/coff/pe.h
@@ -604,7 +604,7 @@ struct external_IMAGE_DEBUG_DIRECTORY
#define CVINFO_PDB70_CVSIGNATURE 0x53445352 // "RSDS"
#define CVINFO_PDB20_CVSIGNATURE 0x3031424e // "NB10"
#define CVINFO_CV50_CVSIGNATURE 0x3131424e // "NB11"
-#define CVINFO_CV41_CVSIGNATURE 0x3930424e // âNB09"
+#define CVINFO_CV41_CVSIGNATURE 0x3930424e // "NB09"
typedef struct _CV_INFO_PDB70
{
diff --git a/include/opcode/xgate.h b/include/opcode/xgate.h
index 737c0d9..ad4dbb1 100644
--- a/include/opcode/xgate.h
+++ b/include/opcode/xgate.h
@@ -29,14 +29,14 @@
#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
/* Access Detail Notation
- V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
- P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
- r — 8-bit data read: lasts for at least one RISC core cycle
- R — 16-bit data read: lasts for at least one RISC core cycle
- w — 8-bit data write: lasts for at least one RISC core cycle
- W — 16-bit data write: lasts for at least one RISC core cycle
- A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
- f — Free cycle: no read or write, lasts for one RISC core cycles. */
+ V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
+ P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
+ r - 8-bit data read: lasts for at least one RISC core cycle
+ R - 16-bit data read: lasts for at least one RISC core cycle
+ w - 8-bit data write: lasts for at least one RISC core cycle
+ W - 16-bit data write: lasts for at least one RISC core cycle
+ A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
+ f - Free cycle: no read or write, lasts for one RISC core cycles. */
#define XGATE_CYCLE_V 0x01
#define XGATE_CYCLE_P 0x02
#define XGATE_CYCLE_r 0x04