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authorDavid Edelsohn <dje.gcc@gmail.com>1996-03-31 21:32:00 +0000
committerDavid Edelsohn <dje.gcc@gmail.com>1996-03-31 21:32:00 +0000
commit4be1b313251bda2b1d12031162de9698f3b9b518 (patch)
tree509fee9c87bc06f0496789fecd772e0584082b69 /include
parent323b430fc4e94627a6ce79fa0686e4732719c32e (diff)
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* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog8
-rw-r--r--include/opcode/sparc.h14
2 files changed, 18 insertions, 4 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 477c300..b2cb26a 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
+
+Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com>
+
+ * sparc.h (O): Mark operand letter as in use.
+
Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com>
* sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index d60c554..dc604c2 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -49,13 +49,18 @@ enum sparc_opcode_arch_val {
/* The highest architecture in the table. */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
+/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
+ insn encoding/decoding. */
+#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
+
/* Table of cpu variants. */
struct sparc_opcode_arch {
const char *name;
/* Mask of sparc_opcode_arch_val's supported.
- EG: For v7 this would be ((1 << v6) | (1 << v7)). */
- /* These are short's because sparc_opcode.architecture is. */
+ EG: For v7 this would be
+ (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
+ These are short's because sparc_opcode.architecture is. */
short supported;
};
@@ -144,7 +149,8 @@ Kinds of operands:
z %icc. (v9)
Z %xcc. (v9)
q Floating point queue.
- r Single register that is both rs1 and rsd.
+ r Single register that is both rs1 and rd.
+ O Single register that is both rs2 and rd.
Q Coprocessor queue.
S Special case.
t Trap base register.
@@ -167,7 +173,7 @@ Kinds of operands:
x OPF field (v9 impdep).
The following chars are unused: (note: ,[] are used as punctuation)
-[OXY3450]
+[XY3450]
*/