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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:57:43 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:57:43 +0100 |
| commit | 047cd301d40288d13e44f3322541ac28ebe06078 (patch) | |
| tree | 4aa6ac53c8f70e677ea23c6627d94c8e914de3aa /include | |
| parent | 165d4950855493dd904a7996e7fcf58880d54219 (diff) | |
| download | gdb-047cd301d40288d13e44f3322541ac28ebe06078.zip gdb-047cd301d40288d13e44f3322541ac28ebe06078.tar.gz gdb-047cd301d40288d13e44f3322541ac28ebe06078.tar.bz2 | |
[AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 80016dc..2bde162 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. + (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) + (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9e7f5b5..8d3fb21 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -310,6 +310,8 @@ enum aarch64_opnd AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ + AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ + AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ @@ -322,6 +324,10 @@ enum aarch64_opnd AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ + AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ + AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ + AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ + AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ |