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| author | Mark Shinwell <shinwell@codesourcery.com> | 2006-10-17 15:46:21 +0000 |
|---|---|---|
| committer | Mark Shinwell <shinwell@codesourcery.com> | 2006-10-17 15:46:21 +0000 |
| commit | e95de06338c51f03d29a7fe5d2f1c374054c9e44 (patch) | |
| tree | c937d392949fca1f00e9a842656b972445a2f5ae /include | |
| parent | 32a5b2f1dd80c5d2d634ebbea7a849b389de5813 (diff) | |
| download | gdb-e95de06338c51f03d29a7fe5d2f1c374054c9e44.zip gdb-e95de06338c51f03d29a7fe5d2f1c374054c9e44.tar.gz gdb-e95de06338c51f03d29a7fe5d2f1c374054c9e44.tar.bz2 | |
bfd/
* elf32-arm.c (elf32_arm_howto_table_1): Change offset for
R_THM_CALL to 25 and remove FIXME comment.
(using_thumb2): New function.
(elf32_arm_final_link_relocate): Cope with Thumb-2 BL encoding.
include/
* elf/arm.h: Define TAG_CPU_ARCH_* constants.
ld/testsuite/
* ld-arm/arm-elf.exp: Add thumb1-bl, thumb2-bl,
thumb2-bl-as-thumb1-bad and thumb2-bl-bad tests.
* ld-arm/thumb1-bl.d: New.
* ld-arm/thumb1-bl.s: New.
* ld-arm/thumb2-bl-as-thumb1-bad.d: New.
* ld-arm/thumb2-bl-as-thumb1-bad.s: New.
* ld-arm/thumb2-bl-bad.d: New.
* ld-arm/thumb2-bl-bad.s: New.
* ld-arm/thumb2-bl.d: New.
* ld-arm/thumb2-bl.s: New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/elf/arm.h | 13 |
2 files changed, 17 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 6c09101..564efea 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2006-10-17 Mark Shinwell <shinwell@codesourcery.com> + + * elf/arm.h: Define TAG_CPU_ARCH_* constants. + 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> * dis-asm.h: Add prototypes for Score disassembler routines. diff --git a/include/elf/arm.h b/include/elf/arm.h index 6b72977..890ef8d 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -84,6 +84,19 @@ #define PF_ARM_PI 0x20000000 /* Segment is position-independent. */ #define PF_ARM_ABS 0x40000000 /* Segment must be loaded at its base address. */ +/* Values for the Tag_CPU_arch EABI attribute. */ +#define TAG_CPU_ARCH_PRE_V4 0 +#define TAG_CPU_ARCH_V4 1 +#define TAG_CPU_ARCH_V4T 2 +#define TAG_CPU_ARCH_V5T 3 +#define TAG_CPU_ARCH_V5TE 4 +#define TAG_CPU_ARCH_V5TEJ 5 +#define TAG_CPU_ARCH_V6 6 +#define TAG_CPU_ARCH_V6KZ 7 +#define TAG_CPU_ARCH_V6T2 8 +#define TAG_CPU_ARCH_V6K 9 +#define TAG_CPU_ARCH_V7 10 + /* Relocation types. */ START_RELOC_NUMBERS (elf_arm_reloc_type) |