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authorMatthew Wahab <matthew.wahab@arm.com>2015-12-15 16:37:38 +0000
committerMatthew Wahab <matthew.wahab@arm.com>2015-12-15 16:38:58 +0000
commit29b1539538f5f285e017adbc64b8d72b45c104a8 (patch)
treebb06a6c73535e8b66c13e8ad551f562887eaea30 /include
parentff1fe6fad9687cebddcdf82076c55d7025df7566 (diff)
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[ARM] Enable CRC by default for ARMv8.1 and later.
ARMv8.1 includes CRC as a required extension but the +crc feature isn't enabled by -march=armv8.1-a as it should be. This patch fixes that. opcode/include 2015-12-15 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor feature macro. (ARM_ARCH_V8_2A): Likewise. Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog6
-rw-r--r--include/opcode/arm.h8
2 files changed, 11 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 7ccd62e..ca7492b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
+ feature macro.
+ (ARM_ARCH_V8_2A): Likewise.
+
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (enum aarch64_opnd_qualifier): Add
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 5e7d683..0814d80 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -251,9 +251,11 @@
#define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M)
#define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM)
#define ARM_ARCH_V8A ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A)
-#define ARM_ARCH_V8_1A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_PAN)
-#define ARM_ARCH_V8_2A ARM_FEATURE_CORE (ARM_AEXT_V8A, \
- ARM_EXT2_PAN | ARM_EXT2_V8_2A)
+#define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
+ CRC_EXT_ARMV8)
+#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, \
+ ARM_EXT2_PAN | ARM_EXT2_V8_2A, \
+ CRC_EXT_ARMV8)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)