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authorNick Clifton <nickc@redhat.com>2013-03-21 16:08:07 +0000
committerNick Clifton <nickc@redhat.com>2013-03-21 16:08:07 +0000
commit81f5558e3d93654ed79b6ea28850a4798ea1404f (patch)
tree09a020b2f58cf3b34739e07297561af0184b61ba /include
parentb2f83c08372136fe9fe7d1df2feb5566c8b883fb (diff)
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* elf32-h8300 (h8_relax_section): Add new relaxation of mov
@(disp:32,ERx) to mov @(disp:16,ERx). (R_H8_DISP32A16): New reloc. Comments added and corrected. * reloc.c (BFD_RELOC_H8_DISP32A16): New reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * ld.texinfo (H8/300): Add description of relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx). * ld-h8300/h8300.exp: Add new relax-7 test on ELF. * ld-h8300/relax-2.s: Add other direction and .w/.l variants of mov insns. * ld-h8300/relax-2.d: Update expected disassembly. * ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov @(disp:16,ERx). * ld-h8300/relax-7b.s: New: Likewise. * ld-h8300/relax-7.d: New: expected disassembly. * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc R_H8_DISP32A16. * config/tc-h8300.h: Remove duplicated defines.
Diffstat (limited to 'include')
-rw-r--r--include/elf/ChangeLog5
-rw-r--r--include/elf/h8.h5
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/h8300.h14
4 files changed, 19 insertions, 10 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index f08ca6b..c7265920 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2013-03-21 Michael Schewe <michael.schewe@gmx.net>
+
+ * h8.h: Add new reloc R_H8_DISP32A16 for relaxation of
+ mov @(disp:32,ERx) to mov @(disp:16,ERx).
+
2013-03-08 Andreas Arnez <arnez@linux.vnet.ibm.com>
* common.h (NT_S390_TDB): Define.
diff --git a/include/elf/h8.h b/include/elf/h8.h
index 36aef6a..2a3d905 100644
--- a/include/elf/h8.h
+++ b/include/elf/h8.h
@@ -1,5 +1,5 @@
/* H8300/h8500 ELF support for BFD.
- Copyright 2001, 2003, 2010 Free Software Foundation, Inc.
+ Copyright 2001-2013 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -23,7 +23,7 @@
#include "elf/reloc-macros.h"
/* Relocations. */
-/* Relocations 59..63 are GNU extensions. */
+/* Relocations 59..64 are GNU extensions. */
START_RELOC_NUMBERS (elf_h8_reloc_type)
RELOC_NUMBER (R_H8_NONE, 0)
RELOC_NUMBER (R_H8_DIR32, 1)
@@ -65,6 +65,7 @@ START_RELOC_NUMBERS (elf_h8_reloc_type)
RELOC_NUMBER (R_H8_DIR24A8, 61)
RELOC_NUMBER (R_H8_DIR24R8, 62)
RELOC_NUMBER (R_H8_DIR32A16, 63)
+ RELOC_NUMBER (R_H8_DISP32A16, 64)
RELOC_NUMBER (R_H8_ABS32, 65)
RELOC_NUMBER (R_H8_ABS32A16, 127)
RELOC_NUMBER (R_H8_SYM, 128)
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index cc7ef5f..bdf990e 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-03-21 Michael Schewe <michael.schewe@gmx.net>
+
+ * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
+ and mov.b/w/l Rs,@(d:32,ERd).
+
2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
PR gas/15082
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 81b1c08..3296deb 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -1,7 +1,5 @@
/* Opcode table for the H8/300
- Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright 1991-2013 Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>.
This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
@@ -553,7 +551,7 @@ struct h8_opcode
{CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \
{CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
+ {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
@@ -571,7 +569,7 @@ struct h8_opcode
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \
{CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \
+ {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
@@ -1518,8 +1516,8 @@ struct h8_opcode h8_opcodes[] =
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
+ {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTDISP32LIST, E}}},
+ {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
@@ -1537,7 +1535,7 @@ struct h8_opcode h8_opcodes[] =
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
+ {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, MEMRELAX | SRC | DISP32LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},