diff options
| author | Nick Clifton <nickc@redhat.com> | 2013-03-27 11:43:37 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2013-03-27 11:43:37 +0000 |
| commit | 51dcdd4d3edac8b0c94257096337cd94b4dc7c3f (patch) | |
| tree | d1b958a9e07e8cc2d9af0e308e1c3058508a841f /include | |
| parent | 6f820c855cf3f858cea1d9284de4e925889476bf (diff) | |
| download | gdb-51dcdd4d3edac8b0c94257096337cd94b4dc7c3f.zip gdb-51dcdd4d3edac8b0c94257096337cd94b4dc7c3f.tar.gz gdb-51dcdd4d3edac8b0c94257096337cd94b4dc7c3f.tar.bz2 | |
PR binutils/15068
* tic6x-dis.c: Add support for displaying 16-bit insns.
* tic6xc-insn-formats.h (FLD): Add use of bitfield array.
Add 16-bit opcodes.
* tic6xc-opcode-table.h: Add 16-bit insns.
* tic6x.h: Add support for 16-bit insns.
* config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
* gas/tic6x/insns16-d-unit.s: New test.
* gas/tic6x/insns16-d-unit.d: Expected disassembly.
* gas/tic6x/insns16-ddec.s: New test.
* gas/tic6x/insns16-ddec.d: Expected disassembly.
* gas/tic6x/insns16-dinc.s: New test.
* gas/tic6x/insns16-dinc.d: Expected disassembly.
* gas/tic6x/insns16-dind.s: New test.
* gas/tic6x/insns16-dind.d: Expected disassembly.
* gas/tic6x/insns16-doff4.s: New test.
* gas/tic6x/insns16-doff4.d: Expected disassembly.
* gas/tic6x/insns16-l-unit.s: New test.
* gas/tic6x/insns16-l-unit.d: Expected disassembly.
* gas/tic6x/insns16-lsd-unit.s: New test.
* gas/tic6x/insns16-lsd-unit.d: Expected disassembly.
* gas/tic6x/insns16-m-unit.s: New test.
* gas/tic6x/insns16-m-unit.d: Expected disassembly.
* gas/tic6x/insns16-s-unit-pcrel.s: New test.
* gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly.
* gas/tic6x/insns16-s-unit: New test.
* gas/tic6x/insns16-s-unit.d: Expected disassembly.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/tic6x-insn-formats.h | 424 | ||||
| -rw-r--r-- | include/opcode/tic6x-opcode-table.h | 1123 | ||||
| -rw-r--r-- | include/opcode/tic6x.h | 114 |
4 files changed, 1659 insertions, 10 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index bdf990e..9f7f157 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR binutils/15068 + * tic6xc-insn-formats.h (FLD): Add use of bitfield array. + Add 16-bit opcodes. + * tic6xc-opcode-table.h: Add 16-bit insns. + * tic6x.h: Add support for 16-bit insns. + 2013-03-21 Michael Schewe <michael.schewe@gmx.net> * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd diff --git a/include/opcode/tic6x-insn-formats.h b/include/opcode/tic6x-insn-formats.h index 8ce2418..80bc9fa 100644 --- a/include/opcode/tic6x-insn-formats.h +++ b/include/opcode/tic6x-insn-formats.h @@ -1,6 +1,5 @@ /* TI C6X instruction format information. - Copyright 2010 - Free Software Foundation, Inc. + Copyright 2010-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -20,7 +19,19 @@ /* Define the FMT macro before including this file; it takes a name and the fields from tic6x_insn_format (defined in tic6x.h). */ -#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) } +/* Expansion fields values for 16 bits insn. */ +#define SAT(a) (((a) & 1) << TIC6X_COMPACT_SAT_POS) +#define BR(a) (((a) & 1) << TIC6X_COMPACT_BR_POS) +#define DSZ(a) (((a) & 7) << TIC6X_COMPACT_DSZ_POS) +/* Composite fields for 16 bits insn. */ +#define BFLD(low_pos, width, pos) { (low_pos), (width), (pos) } +#define BFLD1(a) 1, { a } +#define BFLD2(a, b) 2, { a, b } +#define BFLD3(a, b, c) 3, { a, b, c } +#define BFLD4(a, b, c, d) 4, { a, b, c, d } +#define COMPFLD(name, bitfields) { CONCAT2(tic6x_field_,name), bitfields } +/**/ +#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), BFLD1(BFLD(pos, width, 0)) } #define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1) #define CFLDS2(a, b) 5, { CFLDS, a, b } #define CFLDS3(a, b, c) 6, { CFLDS, a, b, c } @@ -36,6 +47,21 @@ #define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e } #define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f } #define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g } +/* 16 bits insn */ +#define FLDS1(a) 1, { a } +#define FLDS2(a, b) 2, { a, b } +#define FLDS3(a, b, c) 3, { a, b, c } +#define FLDS4(a, b, c, d) 4, { a, b, c, d } +#define FLDS5(a, b, c, d, e) 5, { a, b, c, d, e } +#define SFLDS FLD(s, 0, 1) +#define SFLDS1(a) 2, { SFLDS, a } +#define SFLDS2(a, b) 3, { SFLDS, a, b } +#define SFLDS3(a, b, c) 4, { SFLDS, a, b, c } +#define SFLDS4(a, b, c, d) 5, { SFLDS, a, b, c, d } +#define SFLDS5(a, b, c, d, e) 6, { SFLDS, a, b, c, d, e } +#define SFLDS6(a, b, c, d, e, f) 7, { SFLDS, a, b, c, d, e, f } +#define SFLDS7(a, b, c, d, e, f, g) 8, { SFLDS, a, b, c, d, e, f, g } +/**/ /* These are in the order from SPRUFE8, appendices C-H. */ @@ -68,6 +94,194 @@ FMT(d_adda_long, 32, 0x1000000c, 0xf000000c, /* Appendix C 16-bit formats will go here. */ +/* C-8 */ +FMT(d_doff4_dsz_0xx, 16, DSZ(0) | 0x0004, DSZ(0x4) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_100, 16, DSZ(4) | 0x0004, DSZ(0x7) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_000, 16, DSZ(0) | 0x0004, DSZ(0x7) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_x01, 16, DSZ(1) | 0x0004, DSZ(0x3) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_01x, 16, DSZ(2) | 0x0004, DSZ(0x6) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_111, 16, DSZ(7) | 0x0004, DSZ(0x7) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_x11, 16, DSZ(3) | 0x0004, DSZ(0x3) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_010, 16, DSZ(2) | 0x0004, DSZ(0x7) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) +FMT(d_doff4_dsz_110, 16, DSZ(6) | 0x0004, DSZ(0x7) | 0x0406, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) + +/* C-9 */ +FMT(d_doff4dw, 16, DSZ(4) | 0x0004, DSZ(0x4) | 0x0406, + SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) + +/* C-10 */ +FMT(d_dind_dsz_0xx, 16, DSZ(0) | 0x0404, DSZ(0x4) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_x01, 16, DSZ(1) | 0x0404, DSZ(0x3) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_x11, 16, DSZ(3) | 0x0404, DSZ(0x3) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_01x, 16, DSZ(2) | 0x0404, DSZ(0x6) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_000, 16, DSZ(0) | 0x0404, DSZ(0x7) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_010, 16, DSZ(2) | 0x0404, DSZ(0x7) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_100, 16, DSZ(4) | 0x0404, DSZ(0x7) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_110, 16, DSZ(6) | 0x0404, DSZ(0x7) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +FMT(d_dind_dsz_111, 16, DSZ(7) | 0x0404, DSZ(0x7) | 0x0c06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(src1, 13, 3))) + +/* C-11 */ +FMT(d_dinddw, 16, DSZ(4) | 0x0404, DSZ(0x4) | 0x0c06, + SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), + FLD(sz, 9, 1), FLD(t, 12, 1), FLD(src1, 13, 3))) + +/* C-12 */ +FMT(d_dinc_dsz_x01, 16, DSZ(1) | 0x0c04, DSZ(0x3) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_0xx, 16, DSZ(0) | 0x0c04, DSZ(0x4) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_01x, 16, DSZ(2) | 0x0c04, DSZ(0x6) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_x11,16, DSZ(3) | 0x0c04, DSZ(0x3) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_000, 16, DSZ(0) | 0x0c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_010, 16, DSZ(2) | 0x0c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_100, 16, DSZ(4) | 0x0c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_110, 16, DSZ(6) | 0x0c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_dinc_dsz_111, 16, DSZ(7) | 0x0c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +/* C-13*/ +FMT(d_dincdw, 16, DSZ(4) | 0x0c04, DSZ(0x4) | 0xcc06, + SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), + FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1))) + +/* C-14 */ +FMT(d_ddec_dsz_01x, 16, DSZ(2) | 0x4c04, DSZ(0x6) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_0xx, 16, DSZ(0) | 0x4c04, DSZ(0x4) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_x01, 16, DSZ(1) | 0x4c04, DSZ(0x3) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_x11, 16, DSZ(3) | 0x4c04, DSZ(0x3) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_000, 16, DSZ(0) | 0x4c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_010, 16, DSZ(2) | 0x4c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_100, 16, DSZ(4) | 0x4c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_110, 16, DSZ(6) | 0x4c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +FMT(d_ddec_dsz_111, 16, DSZ(7) | 0x4c04, DSZ(0x7) | 0xcc06, + SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), + FLD(t, 12, 1), FLD(cst, 13, 1))) + +/* C-15 */ +FMT(d_ddecdw, 16, DSZ(4) | 0x4c04, DSZ(0x4) | 0xcc06, + SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), + FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1))) + +/* C-16 */ +FMT(d_dstk, 16, 0x8c04, 0x8c06, + SFLDS4(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(t, 12, 1), + COMPFLD(cst, BFLD2(BFLD(7, 3, 2), BFLD(13, 2, 0))))) + +/* C-17 */ +FMT(d_dx2op, 16, 0x0036, 0x047e, + SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), FLD(srcdst, 13, 3))) + +/* C-18 */ +FMT(d_dx5, 16, 0x0436, 0x047e, + SFLDS2(FLD(dst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* C-19 */ +FMT(d_dx5p, 16, 0x0c76, 0x1c7e, + SFLDS2(FLD(op, 7, 1), + COMPFLD(cst, BFLD2(BFLD(8, 2, 3), BFLD(13, 3, 0))))) + +/* C-20 */ +FMT(d_dx1, 16, 0x1876, 0x1c7e, + SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) + +/* C-21 */ +FMT(d_dpp, 16, 0x0077, 0x087f, + SFLDS5(FLD(srcdst, 7, 4), FLD(t, 12, 1), FLD(cst, 13, 1), FLD(op, 14, 1), + FLD(dw, 15, 1))) + /* Appendix D 32-bit formats. */ FMT(l_1_or_2_src, 32, 0x18, 0x1c, @@ -82,6 +296,44 @@ FMT(l_unary, 32, 0x358, 0xffc, /* Appendix D 16-bit formats will go here. */ +/* D-4 */ +FMT(l_l3_sat_0, 16, SAT(0) | 0x0000, SAT(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +FMT(l_l3_sat_1, 16, SAT(1) | 0x0000, SAT(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +/* D-5 - combine cst3 and n fields into a single field cst */ +FMT(l_l3i, 16, 0x0400, 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(sn, 11, 1), FLD(x, 12, 1), + COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) + +/* D-6 Mtbd ? */ + +/* D-7 */ +FMT(l_l2c, 16, 0x0408, 0x040e, + SFLDS5(FLD(dst, 4, 1), FLD(src2, 7, 3), FLD(x, 12, 1), FLD(src1, 13, 3), + COMPFLD(op, BFLD2(BFLD(5, 2, 0), BFLD(11, 1, 2))))) + +/* D-8 */ +FMT(l_lx5, 16, 0x0426, 0x047e, + SFLDS2(FLD(dst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* D-9 */ +FMT(l_lx3c, 16, 0x0026, 0x147e, + SFLDS3(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 3))) + +/* D-10 */ +FMT(l_lx1c, 16, 0x1026, 0x147e, + SFLDS4(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 1), FLD(op, 14, 2))) + +/* D-11 */ +FMT(l_lx1, 16, 0x1866, 0x1c7e, + SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) + /* Appendix E 32-bit formats. */ FMT(m_compound, 32, 0x30, 0x83c, @@ -101,6 +353,12 @@ FMT(m_mpy, 32, 0x0, 0x7c, FLD(src2, 18, 5), FLD(dst, 23, 5))) /* Appendix E 16-bit formats will go here. */ +FMT(m_m3_sat_0, 16, SAT(0) | 0x001e, SAT(1) | 0x001e, + SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2), + FLD(x, 12, 1), FLD(src1, 13, 3))) +FMT(m_m3_sat_1, 16, SAT(1) | 0x001e, SAT(1) | 0x001e, + SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2), + FLD(x, 12, 1), FLD(src1, 13, 3))) /* Appendix F 32-bit formats. */ @@ -148,7 +406,113 @@ FMT(s_bpos, 32, 0x20, 0x1ffc, /* Appendix F 16-bit formats will go here. */ +/* F-17 Sbs7 Instruction Format */ +FMT(s_sbs7, 16, BR(1) | 0x000a, BR(1) | 0x003e, + SFLDS2(FLD(cst, 6, 7), FLD(n, 13, 3))) + +/* F-18 Sbu8 Instruction Format */ +FMT(s_sbu8, 16, BR(1) | 0xc00a, BR(1) | 0xc03e, + SFLDS1(FLD(cst, 6, 8))) + +/* F-19 Scs10 Instruction Format */ +FMT(s_scs10, 16, BR(1) | 0x001a, BR(1) | 0x003e, + SFLDS1(FLD(cst, 6, 10))) + +/* F-20 Sbs7c Instruction Format */ +FMT(s_sbs7c, 16, BR(1) | 0x002a, BR(1) | 0x002e, + SFLDS3(FLD(z, 4, 1), FLD(cst, 6, 7), FLD(n, 13, 3))) + +/* F-21 Sbu8c Instruction Format */ +FMT(s_sbu8c, 16, BR(1) | 0xc02a, BR(1) | 0xc02e, + SFLDS2(FLD(z, 4, 1), FLD(cst, 6, 8))) + +/* F-22 S3 Instruction Format */ +FMT(s_s3, 16, BR(0) | 0x000a, BR(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +FMT(s_s3_sat_x, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(0) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +FMT(s_s3_sat_0, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +FMT(s_s3_sat_1, 16, BR(0) | SAT(1) | 0x000a, BR(1) | SAT(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(src1, 13, 3))) + +/* F-23 S3i Instruction Format */ +FMT(s_s3i, 16, BR(0) | 0x040a, BR(1) | 0x040e, + SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(cst, 13, 3))) + +/* F-24 Smvk8 Instruction Format */ +FMT(s_smvk8, 16, 0x0012, 0x001e, + SFLDS2(FLD(dst, 7, 3), + COMPFLD(cst, BFLD4(BFLD(10, 1, 7), BFLD(5, 2, 5), BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* F-25 Ssh5 Instruction Format */ +FMT(s_ssh5_sat_x, 16, SAT(0) | 0x0402, SAT(0) | 0x041e, + SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) +FMT(s_ssh5_sat_0, 16, SAT(0) | 0x0402, SAT(1) | 0x041e, + SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) +FMT(s_ssh5_sat_1, 16, SAT(1) | 0x0402, SAT(1) | 0x041e, + SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* F-26 S2sh Instruction Format */ +FMT(s_s2sh, 16, 0x0462, 0x047e, + SFLDS3(FLD(srcdst, 7, 3), FLD(op, 11, 2), FLD(src1, 13, 3))) + +/* F-27 Sc5 Instruction Format */ +FMT(s_sc5, 16, 0x0002, 0x041e, + SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* F-28 S2ext Instruction Format */ +FMT(s_s2ext, 16, 0x0062, 0x047e, + SFLDS3(FLD(src, 7, 3), FLD(op, 11, 2), FLD(dst, 13, 3))) + +/* F-29 Sx2op Instruction Format */ +FMT(s_sx2op, 16, 0x002e, 0x047e, + SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), + FLD(srcdst, 13, 3))) + +/* F-30 Sx5 Instruction Format */ +FMT(s_sx5, 16, 0x042e, 0x047e, + SFLDS2(FLD(dst, 7, 3), + COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0))))) + +/* F-31 Sx1 Instruction Format */ +FMT(s_sx1, 16, 0x186e, 0x1c7e, + SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3))) + +/* F-32 Sx1b Instruction Format */ +FMT(s_sx1b, 16, 0x006e, 0x187e, + SFLDS2(FLD(src2, 7, 4), FLD(n, 13, 3))) + /* Appendix G 16-bit formats will go here. */ +FMT(lsdmvto, 16, 0x0006, 0x0066, + SFLDS4(FLD(unit, 3, 2), + FLD(x, 12, 1), FLD(dst, 13, 3), + COMPFLD(src2, BFLD2(BFLD(10, 2, 3), BFLD(7, 3, 0))))) + +FMT(lsdmvfr, 16, 0x0046, 0x0066, + SFLDS4(FLD(unit, 3, 2), FLD(src2, 7, 3), FLD(x, 12, 1), + COMPFLD(dst, BFLD2(BFLD(10, 2, 3), BFLD(13, 3, 0))))) + +/* G-3 */ +FMT(lsdx1c, 16, 0x0866, 0x1c66, + SFLDS4(FLD(unit, 3, 2), FLD(dst, 7, 3), FLD(cst, 13, 1), + FLD(cc, 14, 2))) + +/* G-4 */ +FMT(lsdx1, 16, 0x1866, 0x1c66, + SFLDS3(FLD(unit, 3, 2), FLD(srcdst, 7, 3), FLD(op, 13, 3))) /* Appendix H 32-bit formats. */ @@ -180,6 +544,38 @@ FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc, /* Appendix H 16-bit formats will go here. */ +/* H-5 */ +FMT(nfu_uspl, 16, 0x0c66, 0xbc7e, + FLDS2(FLD(op, 0, 1), COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3))))) + +/* H-6 */ +/* make up some fields to pretend to have s and z fields s for this format + so as to fit in other predicated compact instruction to avoid special- + casing this instruction in tic6x-dis.c + use op field as a predicate adress register selector (s field) + use the first zeroed bit as a z value as this insn only supports [a0] + and [b0] predicate forms. +*/ +FMT(nfu_uspldr, 16, 0x8c66, 0xbc7e, + FLDS4(FLD(op, 0, 1), FLD(s, 0, 1), FLD(z, 3, 1), + COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3))))) + +/* H-7 */ +FMT(nfu_uspk, 16, 0x1c66, 0x3c7e, + FLDS1(COMPFLD(fstgfcyc, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) + +/* H-8a */ +FMT(nfu_uspma, 16, 0x2c66, 0x3c7e, + FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) + +/* H-8b */ +FMT(nfu_uspmb, 16, 0x3c66, 0x3c7e, + FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4))))) + +/* H-9 */ +FMT(nfu_unop, 16, 0x0c6e, 0x1fff, + FLDS1(FLD(n, 13, 3))) + #undef FLD #undef CFLDS #undef CFLDS2 @@ -196,3 +592,25 @@ FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc, #undef NFLDS5 #undef NFLDS6 #undef NFLDS7 +#undef SFLDS +#undef SFLDS1 +#undef SFLDS2 +#undef SFLDS3 +#undef SFLDS4 +#undef SFLDS5 +#undef SFLDS6 +#undef SFLDS7 +#undef BFLD +#undef BFLD1 +#undef BFLD2 +#undef BFLD3 +#undef BFLD4 +#undef FLDS1 +#undef FLDS2 +#undef FLDS3 +#undef FLDS4 +#undef FLDS5 +#undef COMPFLD +#undef DSZ +#undef BR +#undef SAT diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h index e9cfab9..3b7ee14 100644 --- a/include/opcode/tic6x-opcode-table.h +++ b/include/opcode/tic6x-opcode-table.h @@ -45,14 +45,28 @@ #define OP4(a, b, c, d) 4, { a, b, c, d } #define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCSTM1 { tic6x_operand_hw_const_minus_1, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST0 { tic6x_operand_hw_const_0, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST1 { tic6x_operand_hw_const_1, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST5 { tic6x_operand_hw_const_5, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST16 { tic6x_operand_hw_const_16, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST24 { tic6x_operand_hw_const_24, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OHWCST31 { tic6x_operand_hw_const_31, 0, tic6x_rw_none, 0, 0, 0, 0 } #define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 } #define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define OWREG1Z { tic6x_operand_zreg, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define OWREG1NORS { tic6x_operand_reg_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define ORREG1B { tic6x_operand_reg_bside, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define ORREG1BNORS { tic6x_operand_reg_bside_nors, 4, tic6x_rw_write, 1, 1, 0, 0 } #define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORTREG1 { tic6x_operand_treg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 } +#define ORB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define OWB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 } #define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 } @@ -62,6 +76,7 @@ #define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 } #define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 } #define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 } +#define OWTREG5 { tic6x_operand_treg, 4, tic6x_rw_write, 5, 5, 0, 0 } #define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 } #define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 } #define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 } @@ -71,7 +86,9 @@ #define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 } #define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 } #define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } +#define ORTREGD1 { tic6x_operand_tregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } #define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } +#define OWTREGD5 { tic6x_operand_tregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } #define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } @@ -79,6 +96,7 @@ #define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } #define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define OWILC1 { tic6x_operand_ilc, 4, tic6x_rw_write, 1, 1, 0, 0 } #define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 } #define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 } #define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 } @@ -197,6 +215,55 @@ INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, scst, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(add, l, l3_sat_0, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(add, l, l3i, 1cycle, C64XP, 0, + FIX0(), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(cst, scst_l3i, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(add, l, lx1, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3)), + OP3(OHWCSTM1, ORREG1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) +INSN(add, s, s3_sat_0, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(add, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3)), + OP3(OHWCSTM1, ORREG1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) +INSN(add, s, sx2op, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), + ENC(src2, reg, 1), ENC(x, xpath, 1))) +INSN(add, d, dx2op, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0), + ENC(src2, reg, 1), ENC(srcdst, reg, 2))) +INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x0)), + OP3(ORREG1, OHWCST1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x1)), + OP3(ORREG1, OHWCST1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x2)), + OP3(ORREG1, OHWCST1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +/**/ + INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x30)), OP3(ORREG1, ORREG1, OWREG1), @@ -261,6 +328,17 @@ INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(addaw, d, dx5, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, + FIX0(), + OP3(ORB15REG1, OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 1), ENC(dst, reg, 2))) +INSN(addaw, d, dx5p, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE, + FIX1(FIX(op, 0)), + OP3(ORB15REG1, OACST, OWB15REG1), + ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1))) +/**/ + INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0, FIX1(FIX(op, 0x18)), OP3(ORREGD12, ORXREGD12, OWREGD67), @@ -277,6 +355,13 @@ INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, OP2(OLCST, OWREG1), ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(addk, s, sx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) +/**/ + INSN(addkpc, s, addkpc, 1cycle, C64X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY, FIX1(FIX(s, 1)), @@ -370,6 +455,14 @@ INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(and, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 0)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7c)), OP3(ORREG1, ORXREG1, OWREG1), @@ -448,6 +541,34 @@ INSN(bnop, s, branch_nop_reg, branch, C64X, OP2(ORXREG1, OACST), ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) +/* 16 bits insn format */ +INSN(bnop, s, sbu8, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX0(), + OP2(OLCST, OHWCST5), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0))) +INSN(bnop, s, sbs7, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX0(), + OP2(OLCST, OACST), + ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1))) +INSN(bnop, s, sbu8c, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED, + FIX0(), + OP2(OLCST, OHWCST5), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0))) +INSN(bnop, s, sbs7c, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED, + FIX0(), + OP2(OLCST, OACST), + ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1))) +INSN(bnop, s, sx1b, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX0(), + OP2(ORREG1BNORS, OACST), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(n, ucst, 1))) +/**/ + INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS, FIX0(), OP2(OLCST, ORREG1), @@ -490,12 +611,21 @@ INSN(callnop, s, branch_nop_reg, branch, C64X, OP2(ORXREG1, OACST), ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) + INSN(callp, s, call_imm_nop, branch, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, FIX1(FIX(z, 1)), OP2(OLCST, OWRETREG1), ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +/* 16 bits insn format */ +INSN(callp, s, scs10, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX0(), + OP2(OLCST, OWRETREG1), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +/**/ + INSN(callret, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, FIX0(), @@ -528,6 +658,14 @@ INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(clr, s, sc5, 1cycle, C64XP, 0, + FIX1(FIX(op, 2)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1), + ENC(cst, ucst, 2), ENC(srcdst, reg, 3))) +/**/ + INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x53)), OP3(ORREG1, ORXREG1, OWREG1), @@ -549,6 +687,20 @@ INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(cmpeq, l, lx3c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP3(OACST, ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +INSN(cmpeq, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 3)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x1d)), OP3(ORREG1, ORXREG1, OWREG1), @@ -616,6 +768,19 @@ INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(cmpgt, l, lx1c, 1cycle, C64XP, 0, + FIX1(FIX(op, 1)), + OP3(OACST, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSN(cmpgt, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 5)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x14)), OP3(ORREG1, ORXREG1, OWREG1), @@ -668,6 +833,19 @@ INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(cmpgtu, l, lx1c, 1cycle, C64XP, 0, + FIX1(FIX(op, 3)), + OP3(OACST, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSN(cmpgtu, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 7)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x15)), OP3(ORREG1, ORXREG1, OWREG1), @@ -717,6 +895,19 @@ INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(cmplt, l, lx1c, 1cycle, C64XP, 0, + FIX1(FIX(op, 0)), + OP3(OACST, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSN(cmplt, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 4)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, FIX1(FIX(op, 0x14)), OP3(ORXREG1, ORREG1, OWREG1), @@ -767,6 +958,19 @@ INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(cmpltu, l, lx1c, 1cycle, C64XP, 0, + FIX1(FIX(op, 2)), + OP3(OACST, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSN(cmpltu, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 6)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, FIX1(FIX(op, 0x15)), OP3(ORXREG1, ORREG1, OWREG1), @@ -944,6 +1148,17 @@ INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSNE(ext, hwcst16, s, s2ext, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP4(ORREG1, OHWCST16, OHWCST16, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) +INSNE(ext, hwcst24, s, s2ext, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP4(ORREG1, OHWCST24, OHWCST24, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) +/**/ + INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x0)), OP4(ORREG1, OACST, OACST, OWREG1), @@ -955,6 +1170,21 @@ INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSNE(extu, hwcst16, s, s2ext, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x2)), + OP4(ORREG1, OHWCST16, OHWCST16, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) +INSNE(extu, hwcst24, s, s2ext, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x3)), + OP4(ORREG1, OHWCST24, OHWCST24, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3))) +INSN(extu, s, sc5, 1cycle, C64XP, 0, + FIX1(FIX(op, 0)), + OP4(ORREG1, OACST, OHWCST31, OWREG1Z), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1))) +/**/ + INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x1f), FIX(x, 0)), OP3(ORREG1, ORREG1, OWREG4), @@ -1012,6 +1242,33 @@ INSN(ldb, d, load_store_long, load, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(ldb, d, doff4_dsz_x01, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) +INSN(ldb, d, dind_dsz_x01, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldb, d, dinc_dsz_x01, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldb, d, ddec_dsz_x01, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +/**/ + INSN(ldbu, d, load_store, load, C62X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 1), FIX(r, 0)), @@ -1026,6 +1283,33 @@ INSN(ldbu, d, load_store_long, load, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(ldbu, d, dinc_dsz_000, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +INSN(ldbu, d, dind_dsz_000, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +INSN(ldbu, d, doff4_dsz_000, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +INSN(ldbu, d, ddec_dsz_000, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSB, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +/**/ + INSN(lddw, d, load_store, load, C64X_AND_C67X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 6), FIX(r, 1)), @@ -1034,6 +1318,39 @@ INSN(lddw, d, load_store, load, C64X_AND_C67X, ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), ENC(srcdst, reg, 1))) +/* 16 bits insn */ +INSN(lddw, d, dpp, load, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, + FIX2(FIX(op, 1), FIX(dw, 1)), + OP2(ORMEMSD, OWDREGD5), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(cst, mem_offset_minus_one, 0))) +INSN(lddw, d, ddecdw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), + OP2(ORMEMSD, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(lddw, d, dincdw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), + OP2(ORMEMSD, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(lddw, d, dinddw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), + OP2(ORMEMSD, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) +INSN(lddw, d, doff4dw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)), + OP2(ORMEMSD, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) +/**/ + INSN(ldh, d, load_store, load, C62X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 4), FIX(r, 0)), @@ -1048,6 +1365,33 @@ INSN(ldh, d, load_store_long, load, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(ldh, d, doff4_dsz_x11, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +INSN(ldh, d, dind_dsz_x11, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldh, d, dinc_dsz_x11, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldh, d, ddec_dsz_x11, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +/**/ + INSN(ldhu, d, load_store, load, C62X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 0), FIX(r, 0)), @@ -1062,6 +1406,33 @@ INSN(ldhu, d, load_store_long, load, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(ldhu, d, doff4_dsz_010, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1))) +INSN(ldhu, d, dind_dsz_010, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldhu, d, dinc_dsz_010, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldhu, d, ddec_dsz_010, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSH, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +/**/ + INSN(ldndw, d, load_nonaligned, load, C64X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, FIX0(), @@ -1070,6 +1441,33 @@ INSN(ldndw, d, load_nonaligned, load, C64X, ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0), ENC(sc, scaled, 0), ENC(dst, reg_shift, 1))) +/* 16 bits insn */ +INSN(ldndw, d, ddecdw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), + OP2(ORMEMND, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0))) +INSN(ldndw, d, dincdw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), + OP2(ORMEMND, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0))) +INSN(ldndw, d, dinddw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), + OP2(ORMEMND, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) +INSN(ldndw, d, doff4dw, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)), + OP2(ORMEMND, OWTREGD5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 0), + ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1))) +/**/ + INSN(ldnw, d, load_store, load, C64X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, FIX2(FIX(op, 3), FIX(r, 1)), @@ -1078,6 +1476,33 @@ INSN(ldnw, d, load_store, load, C64X, ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), ENC(srcdst, reg, 1))) +/* 16 bits insn */ +INSN(ldnw, d, doff4_dsz_110, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) +INSN(ldnw, d, dind_dsz_110, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldnw, d, dinc_dsz_110, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldnw, d, ddec_dsz_110, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +/**/ + INSN(ldw, d, load_store, load, C62X, TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 6), FIX(r, 0)), @@ -1092,6 +1517,69 @@ INSN(ldw, d, load_store_long, load, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(ldw, d, doff4_dsz_0xx, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 0)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) +INSN(ldw, d, doff4_dsz_100, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0))) +INSN(ldw, d, dind_dsz_0xx, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 0)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldw, d, dind_dsz_100, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0))) +INSN(ldw, d, dinc_dsz_0xx, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 0)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldw, d, dinc_dsz_100, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldw, d, ddec_dsz_0xx, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 0)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldw, d, ddec_dsz_100, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 1), FIX(sz, 1)), + OP2(ORMEMSW, OWTREG5), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0))) +INSN(ldw, d, dpp, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, + FIX2(FIX(op, 1), FIX(dw, 0)), + OP2(ORMEMSW, OWTREG5), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(cst, mem_offset_minus_one, 0))) +INSN(ldw, d, dstk, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR, + FIX2(FIX(op, 0x1), FIX(s, 1)), + OP2(ORMEMSW, OWTREG5), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), + ENC(cst, mem_offset, 0))) +/**/ + INSN(ll, d, 1_or_2_src, load, C64XP, TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)), @@ -1154,6 +1642,13 @@ INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16-bit insn. */ +INSN(mpy, m, m3_sat_0, 1616_m, C67X, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) + INSN(mpydp, m, mpy, mpydp, C67X, 0, FIX1(FIX(op, 0x0e)), OP3(ORREGD1234, ORXREGD1324, OWREGD910), @@ -1166,6 +1661,14 @@ INSN(mpyh, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(mpyh, m, m3_sat_0, 1616_m, C67X, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(mpyhi, m, compound, 4cycle, C64X, 0, FIX1(FIX(op, 0x14)), OP3(ORREG1, ORXREG1, OWREGD4), @@ -1184,6 +1687,14 @@ INSN(mpyhl, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(mpyhl, m, m3_sat_0, 1616_m, C67X, 0, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(mpyhlu, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x0f)), OP3(ORREG1, ORXREG1, OWREG2), @@ -1272,6 +1783,14 @@ INSN(mpylh, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(mpylh, m, m3_sat_0, 1616_m, C67X, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(mpylhu, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x17)), OP3(ORREG1, ORXREG1, OWREG2), @@ -1435,6 +1954,38 @@ INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSNU(mv, l, lsdmvto, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) + +INSNU(mv, s, lsdmvto, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x1)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) + +INSNU(mv, d, lsdmvto, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x2)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) + +INSNU(mv, l, lsdmvfr, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) + +INSNU(mv, s, lsdmvfr, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x1)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) + +INSNU(mv, d, lsdmvfr, 1cycle, C64X, 0, + FIX1(FIX(unit, 0x2)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1))) +/**/ + INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS, FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)), @@ -1446,6 +1997,14 @@ INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY, ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1), ENC(dst, crlo, 1))) +/* 16 bits insn */ +INSN(mvc, s, sx1, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x6)), + OP2(ORREG1B, OWILC1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 0))) +/**/ + INSN(mvd, m, unary, 4cycle, C64X, 0, FIX1(FIX(op, 0x1a)), OP2(ORXREG1, OWREG4), @@ -1465,6 +2024,53 @@ INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, OP2(OACST, OWREG1), ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1))) +/* 16 bits insn */ +INSN(mvk, l, lx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) +INSN(mvk, s, smvk8, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) +INSNU(mvk, l, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, + FIX1(FIX(unit, 0x0)), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) +INSNU(mvk, s, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, + FIX1(FIX(unit, 0x1)), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) +INSNU(mvk, d, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED, + FIX1(FIX(unit, 0x2)), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1))) +INSNUE(mvk, zero, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0), FIX(unit, 0x0)), + OP2(OHWCST0, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +INSNUE(mvk, zero, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0), FIX(unit, 0x1)), + OP2(OHWCST0, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +INSNUE(mvk, zero, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0), FIX(unit, 0x2)), + OP2(OHWCST0, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +INSNUE(mvk, one, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 1), FIX(unit, 0x0)), + OP2(OHWCST1, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +INSNUE(mvk, one, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 1), FIX(unit, 0x1)), + OP2(OHWCST1, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +INSNUE(mvk, one, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 1), FIX(unit, 0x2)), + OP2(OHWCST1, OWREG1), + ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1))) +/**/ + INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(h, 1)), OP2(OLCST, OWREG1), @@ -1506,6 +2112,15 @@ INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO, OP0(), ENC0()) +/* 16 bits insn */ +/* contrary to sprufe8b.pdf p767, and accordingly to + * dis6x.exe output, unop3 opcode is decoded as NOP N3 + 1 */ +INSN(nop, nfu, unop, nop, C64XP, 0, + FIX0(), + OP1(OACST), + ENC1(ENC(n, ucst_minus_one, 0))) +/**/ + INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, FIX2(FIX(op, 0x63), FIX(src1, 0)), OP2(ORXREG1, OWREG1), @@ -1563,6 +2178,14 @@ INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(or, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 1)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), @@ -1718,6 +2341,20 @@ INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(sadd, l, l3_sat_1, 1cycle, C64XP, 0, + FIX1(FIX(op, 0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(sadd, s, s3_sat_1, 1cycle, C64XP,0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x0)), OP3(ORREG1, ORXREG1, OWREG1), @@ -1770,6 +2407,14 @@ INSN(set, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(set, s, sc5, 1cycle, C64XP, 0, + FIX1(FIX(op, 1)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1), + ENC(cst, ucst, 2), ENC(srcdst, reg, 3))) +/**/ + INSN(shfl, m, unary, 1616_m, C64X, 0, FIX1(FIX(op, 0x1c)), OP2(ORXREG1, OWREG2), @@ -1813,6 +2458,25 @@ INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) +/* 16bit insn */ +INSN(shl, s, s3i, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(cst, cst_s3i, 1), ENC(dst, reg, 2))) +INSN(shl, s, ssh5_sat_x, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), + ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) +INSN(shl, s, s2sh, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), + ENC(srcdst, reg, 2))) +/**/ + INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x61)), OP3(ORREG1, ORXREG1, OWREG1), @@ -1845,6 +2509,25 @@ INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) +/* 16bit insn */ +INSN(shr, s, s3i, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(cst, cst_s3i, 1), ENC(dst, reg, 2))) +INSN(shr, s, ssh5_sat_x, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), + ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) +INSN(shr, s, s2sh, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), + ENC(srcdst, reg, 2))) +/**/ + INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x7)), OP3(ORXREG1, ORREG1, OWREG1), @@ -1888,6 +2571,20 @@ INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(shru, s, ssh5_sat_0, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), + ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) +INSN(shru, s, s2sh, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), + ENC(srcdst, reg, 2))) +/**/ + INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0, FIX1(FIX(op, 0x8)), OP3(ORXREG1, ORREG1, OWREG1), @@ -1911,24 +2608,56 @@ INSN(smpy, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(smpy, m, m3_sat_1, 1616_m, C67X, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(smpyh, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x02)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(smpyh, m, m3_sat_1, 1616_m, C67X, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(smpyhl, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x0a)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(smpyhl, m, m3_sat_1, 1616_m, C67X, 0, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(smpylh, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x12)), OP3(ORREG1, ORXREG1, OWREG2), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(smpylh, m, m3_sat_1, 1616_m, C67X, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg_shift, 2))) +/**/ + INSN(smpy2, m, compound, 4cycle, C64X, 0, FIX1(FIX(op, 0x01)), OP3(ORREG1, ORXREG1, OWREGD4), @@ -1978,6 +2707,14 @@ INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP, OP0(), ENC0()) +/* 16 bits insn */ +INSN(spkernel, nfu, uspk, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, + FIX0(), + OP2(OACST, OACST), + ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1))) +/**/ + INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, FIX1(FIX(s, 0)), @@ -2002,6 +2739,27 @@ INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP, OP1(OACST), ENC1(ENC(cstb, ucst_minus_one, 0))) +/* 16 bits insn */ +INSN(sploop, nfu, uspl, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, + FIX1(FIX(op, 0)), + OP1(OACST), + ENC1(ENC(ii, ucst_minus_one, 0))) + +INSN(sploopd, nfu, uspl, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, + FIX1(FIX(op, 1)), + OP1(OACST), + ENC1(ENC(ii, ucst_minus_one, 0))) + +INSN(sploopd, nfu, uspldr, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP|TIC6X_FLAG_INSN16_SPRED, + FIX0(), + OP1(OACST), + ENC1(ENC(ii, ucst_minus_one, 0))) +/**/ + + /* Contrary to SPRUFE8, this is the correct encoding for this instruction. */ INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, @@ -2009,11 +2767,25 @@ INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, OP1(OFULIST), ENC1(ENC(mask, spmask, 0))) +/* 16 bits insn */ +INSN(spmask, nfu, uspma, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, + FIX0(), + OP1(OFULIST), + ENC1(ENC(mask, spmask, 0))) +/**/ + INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, FIX2(FIX(s, 0), FIX(op, 0x9)), OP1(OFULIST), ENC1(ENC(mask, spmask, 0))) +/* 16 bits insn */ +INSN(spmaskr, nfu, uspmb, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, + FIX0(), + OP1(OFULIST), + ENC1(ENC(mask, spmask, 0))) +/**/ + INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0, FIX2(FIX(op, 0x0b), FIX(src1, 0)), OP2(ORXREG1, OWREG4), @@ -2031,6 +2803,20 @@ INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(sshl, s, ssh5_sat_1, 1cycle, C64XP, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), + ENC(cst, ucst, 1), ENC(srcdst, reg, 2))) +INSN(sshl, s, s2sh, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1), + ENC(srcdst, reg, 2))) +/**/ + INSN(sshvl, m, compound, 1616_m, C64X, 0, FIX1(FIX(op, 0x1c)), OP3(ORXREG1, ORREG1, OWREG2), @@ -2066,6 +2852,14 @@ INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(ssub, l, l3_sat_1, 1cycle, C64XP, 0, + FIX1(FIX(op, 1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/**/ + INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0, FIX1(FIX(op, 0x64)), OP3(ORREG1, ORXREG1, OWREG1), @@ -2086,6 +2880,57 @@ INSN(stb, d, load_store_long, store, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1), ENC(dst, reg, 0))) +/* 16 bits insn */ +INSN(stb, d, doff4_dsz_000, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(stb, d, doff4_dsz_x01, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(stb, d, dind_dsz_000, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0))) +INSN(stb, d, dind_dsz_x01, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0))) +INSN(stb, d, dinc_dsz_000, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stb, d, dinc_dsz_x01, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stb, d, ddec_dsz_000, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stb, d, ddec_dsz_x01, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSB), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +/**/ + INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 4), FIX(r, 1)), OP2(ORDREGD1, OWMEMSD), @@ -2093,6 +2938,39 @@ INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS, ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), ENC(srcdst, reg, 0))) +/* 16 bits insn */ +INSN(stdw, d, dpp, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, + FIX3(FIX(op, 0), FIX(dw, 1), FIX(s, 1)), + OP2(ORTREGD1, OWMEMSD), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(cst, mem_offset_minus_one, 1))) +INSN(stdw, d, ddecdw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMSD), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stdw, d, dincdw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMSD), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stdw, d, dinddw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMSD), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) +INSN(stdw, d, doff4dw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMSD), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) +/**/ + INSN(sth, d, load_store, store, C62X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 5), FIX(r, 0)), @@ -2107,6 +2985,57 @@ INSN(sth, d, load_store_long, store, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1), ENC(dst, reg, 0))) +/* 16 bits insn */ +INSN(sth, d, doff4_dsz_01x, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(sth, d, doff4_dsz_111, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(sth, d, dind_dsz_01x, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) +INSN(sth, d, dind_dsz_111, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) +INSN(sth, d, dinc_dsz_01x, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(sth, d, dinc_dsz_111, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(sth, d, ddec_dsz_01x, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(sth, d, ddec_dsz_111, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSH), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +/**/ + INSN(stndw, d, store_nonaligned, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, FIX0(), @@ -2115,6 +3044,33 @@ INSN(stndw, d, store_nonaligned, store, C64X, ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1), ENC(sc, scaled, 1), ENC(src, reg_shift, 0))) +/* 16 bits insn */ +INSN(stndw, d, ddecdw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMND), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1))) +INSN(stndw, d, dincdw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMND), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1))) +INSN(stndw, d, dinddw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMND), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) +INSN(stndw, d, doff4dw, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)), + OP2(ORTREGD1, OWMEMND), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 1), + ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0))) +/**/ + INSN(stnw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, FIX2(FIX(op, 5), FIX(r, 1)), @@ -2123,6 +3079,33 @@ INSN(stnw, d, load_store, store, C64X, ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), ENC(srcdst, reg, 0))) +/* 16 bits insn */ +INSN(stnw, d, doff4_dsz_110, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(stnw, d, dind_dsz_110, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) +INSN(stnw, d, dinc_dsz_110, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stnw, d, ddec_dsz_110, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +/**/ + INSN(stw, d, load_store, store, C62X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), FIX2(FIX(op, 7), FIX(r, 0)), @@ -2137,6 +3120,69 @@ INSN(stw, d, load_store_long, store, C62X, ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1), ENC(dst, reg, 0))) +/* 16 bits insn */ +INSN(stw, d, doff4_dsz_0xx, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 0)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(stw, d, doff4_dsz_100, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1))) +INSN(stw, d, dind_dsz_0xx, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 0)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) +INSN(stw, d, dind_dsz_100, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1))) +INSN(stw, d, dinc_dsz_0xx, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 0)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stw, d, dinc_dsz_100, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stw, d, ddec_dsz_0xx, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 0)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stw, d, ddec_dsz_100, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR), + FIX2(FIX(op, 0), FIX(sz, 1)), + OP2(ORTREG1, OWMEMSW), + ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1))) +INSN(stw, d, dpp, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, + FIX2(FIX(op, 0), FIX(dw, 0)), + OP2(ORTREG1, OWMEMSW), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(cst, mem_offset_minus_one, 1))) +INSN(stw, d, dstk, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR, + FIX2(FIX(op, 0x0), FIX(s, 1)), + OP2(ORTREG1, OWMEMSW), + ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0), + ENC(cst, mem_offset, 1))) +/**/ + INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), FIX1(FIX(op, 0x07)), OP3(ORREG1, ORXREG1, OWREG1), @@ -2217,6 +3263,41 @@ INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(sub, l, l3_sat_0, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(sub, l, lx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2)), + OP3(OHWCST0, ORREG1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) +INSN(sub, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2)), + OP3(OHWCST0, ORREG1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2))) +INSN(sub, s, sx2op, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2), + ENC(src2, reg, 1), ENC(x, xpath, 1))) +INSN(sub, s, s3_sat_x, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(sub, d, dx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, OHWCST1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +INSN(sub, d, dx2op, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(srcdst, reg, 0), + ENC(src2, reg, 1), ENC(srcdst, reg, 2))) +/**/ + INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, FIX1(FIX(op, 0x31)), OP3(ORREG1, ORREG1, OWREG1), @@ -2256,6 +3337,13 @@ INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(subaw, d, dx5p, 1cycle, C64XP, 0, + FIX1(FIX(op, 1)), + OP3(ORB15REG1, OACST, OWB15REG1), + ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1))) +/**/ + INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0, FIX1(FIX(op, 0x4b)), OP3(ORREG1, ORXREG1, OWREG1), @@ -2423,6 +3511,26 @@ INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* 16 bits insn */ +INSN(xor, l, l2c, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG1NORS), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNU(xor, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x0)), + OP3(ORREG1, OHWCST0, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +INSNU(xor, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x1)), + OP3(ORREG1, OHWCST0, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +INSNU(xor, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x7), FIX(unit, 0x2)), + OP3(ORREG1, OHWCST0, OWREG1), + ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) +/**/ + INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0, FIX1(FIX(op, 0x1b)), OP3(ORREG1, ORXREG1, OWREG4), @@ -2491,6 +3599,13 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, #undef OP4 #undef OACST #undef OLCST +#undef OHWCSTM1 +#undef OHWCST0 +#undef OHWCST1 +#undef OHWCST5 +#undef OHWCST16 +#undef OHWCST24 +#undef OHWCST31 #undef OFULIST #undef ORIRP1 #undef ORNRP1 @@ -2511,6 +3626,10 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, #undef OWREGL1 #undef ORREGL1 #undef OWREGD1 +#undef ORTREG1 +#undef ORTREGD1 +#undef OWTREG5 +#undef OWTREGD5 #undef OWREGD12 #undef OWREGD4 #undef ORREGD1 @@ -2523,8 +3642,12 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, #undef ORXREGD1234 #undef ORREGD1324 #undef OWREGD910 +#undef OWILC1 #undef ORCREG1 #undef OWCREG1 +#undef OWREG1Z +#undef ORB15REG1 +#undef OWB15REG1 #undef ORMEMDW #undef OWMEMDW #undef ORMEMSB diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h index 168f660..d76c5e1 100644 --- a/include/opcode/tic6x.h +++ b/include/opcode/tic6x.h @@ -27,18 +27,25 @@ typedef enum { tic6x_field_baseR, + tic6x_field_cc, tic6x_field_creg, tic6x_field_cst, tic6x_field_csta, tic6x_field_cstb, tic6x_field_dst, + tic6x_field_dstms, + tic6x_field_dw, tic6x_field_fstgfcyc, tic6x_field_h, + tic6x_field_ii, tic6x_field_mask, tic6x_field_mode, + tic6x_field_n, + tic6x_field_na, tic6x_field_offsetR, tic6x_field_op, tic6x_field_p, + tic6x_field_ptr, tic6x_field_r, tic6x_field_s, tic6x_field_sc, @@ -46,6 +53,11 @@ typedef enum tic6x_field_src1, tic6x_field_src2, tic6x_field_srcdst, + tic6x_field_srcms, + tic6x_field_sn, + tic6x_field_sz, + tic6x_field_unit, + tic6x_field_t, tic6x_field_x, tic6x_field_y, tic6x_field_z @@ -53,14 +65,24 @@ typedef enum typedef struct { - /* The name used to reference the field. */ - tic6x_insn_field_id field_id; - /* The least-significant bit position in the field. */ - unsigned short low_pos; + unsigned short low_pos; /* The number of bits in the field. */ unsigned short width; + /* The position of the bitfield in the field. */ + unsigned short pos; +} tic6x_bitfield; + +/* Maximum number of subfields in composite field. */ +#define TIC6X_MAX_BITFIELDS 4 + +typedef struct +{ + /* The name used to reference the field. */ + tic6x_insn_field_id field_id; + unsigned int num_bitfields; + tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS]; } tic6x_insn_field; /* Maximum number of variable fields in an instruction format. */ @@ -119,6 +141,13 @@ typedef struct unsigned int max_val; } tic6x_fixed_field; +/* Pseudo opcode fields position for compact instructions + If 16 bits instruction detected, the opcode is enriched + [DSZ/3][BR][SAT][opcode] */ +#define TIC6X_COMPACT_SAT_POS 16 +#define TIC6X_COMPACT_BR_POS 17 +#define TIC6X_COMPACT_DSZ_POS 18 + /* Bit-masks for defining instructions present on some subset of processors; each indicates an instruction present on that processor and those that are supersets of it. The options passed to the @@ -188,6 +217,29 @@ typedef struct values here. */ #define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15) #define TIC6X_FLAG_PREFER(n) ((n) << 15) + +/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */ +#define TIC6X_FLAG_INSN16_SPRED 0x00100000 +/* 16 bits opcode ignores RS bit of fetch packet header */ +#define TIC6X_FLAG_INSN16_NORS 0x00200000 +/* 16 bits opcode only on side B */ +#define TIC6X_FLAG_INSN16_BSIDE 0x00400000 +/* 16 bits opcode ptr reg is b15 */ +#define TIC6X_FLAG_INSN16_B15PTR 0x00800000 +/* 16 bits opcode memory access modes */ +#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16) +#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16) +#define TIC6X_MEM_MODE_NEGATIVE 0 +#define TIC6X_MEM_MODE_POSITIVE 1 +#define TIC6X_MEM_MODE_REG_NEGATIVE 4 +#define TIC6X_MEM_MODE_REG_POSITIVE 5 +#define TIC6X_MEM_MODE_PREDECR 8 +#define TIC6X_MEM_MODE_PREINCR 9 +#define TIC6X_MEM_MODE_POSTDECR 10 +#define TIC6X_MEM_MODE_POSTINCR 11 + +#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode) + #define TIC6X_NUM_PREFER 2 /* Maximum number of fixed fields for a particular opcode. */ @@ -230,6 +282,13 @@ typedef enum /* A register, from the same side as the functional unit selected. */ tic6x_operand_reg, + /* A register, from the same side as the functional unit + selected that ignore RS header bit */ + tic6x_operand_reg_nors, + /* A register, from the b side */ + tic6x_operand_reg_bside, + /* A register, from the b side and from the low register set */ + tic6x_operand_reg_bside_nors, /* A register, that is from the other side if a cross path is used. */ tic6x_operand_xreg, @@ -241,6 +300,14 @@ typedef enum path is not used, and the other side if a cross path is used. */ tic6x_operand_areg, + /* The B15 register */ + tic6x_operand_b15reg, + /* A register coded as an offset from either A16 or B16 depending + on the value of the t bit. */ + tic6x_operand_treg, + /* A register (A0 or B0), from the same side as the + functional unit selected. */ + tic6x_operand_zreg, /* A return address register (A3 or B3), from the same side as the functional unit selected. */ tic6x_operand_retreg, @@ -252,10 +319,15 @@ typedef enum tic6x_operand_xregpair, /* A register pair, from the side of the data path selected. */ tic6x_operand_dregpair, + /* A register pair coded as an offset from either A16 or B16 depending + on the value of the t bit. */ + tic6x_operand_tregpair, /* The literal string "irp" (case-insensitive). */ tic6x_operand_irp, /* The literal string "nrp" (case-insensitive). */ tic6x_operand_nrp, + /* The literal string "ilc" (case-insensitive). */ + tic6x_operand_ilc, /* A control register. */ tic6x_operand_ctrl, /* A memory reference (base and offset registers from the side of @@ -277,7 +349,16 @@ typedef enum tic6x_operand_mem_deref, /* A functional unit name or a list thereof (for SPMASK and SPMASKR). */ - tic6x_operand_func_unit + tic6x_operand_func_unit, + /* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits + instruction formats - spru732j.pdf Appendix F.4 */ + tic6x_operand_hw_const_minus_1, + tic6x_operand_hw_const_0, + tic6x_operand_hw_const_1, + tic6x_operand_hw_const_5, + tic6x_operand_hw_const_16, + tic6x_operand_hw_const_24, + tic6x_operand_hw_const_31 } tic6x_operand_form; /* Whether something is, or can be, read or written. */ @@ -375,6 +456,8 @@ typedef enum /* Likewise, but counting in half-words if in a header-based fetch packet. */ tic6x_coding_pcrel_half, + /* Store an unsigned PC-relative value used in compact insn */ + tic6x_coding_pcrel_half_unsigned, /* Encode the register number (even number for a register pair) in the field. When applied to a memory reference, encode the base register. */ @@ -388,6 +471,8 @@ typedef enum /* Store 0 for register B14, 1 for register B15. When applied to a memory reference, encode the base register. */ tic6x_coding_areg, + /* Compact instruction offset base register */ + tic6x_coding_reg_ptr, /* Store the low part of a control register address. */ tic6x_coding_crlo, /* Store the high part of a control register address. */ @@ -435,7 +520,16 @@ typedef enum destination for load) is on side B, 0 for side A. */ tic6x_coding_data_fu, /* Store 1 if the cross path is being used, 0 otherwise. */ - tic6x_coding_xpath + tic6x_coding_xpath, + /* L3i constant coding */ + tic6x_coding_scst_l3i, + /* S3i constant coding */ + tic6x_coding_cst_s3i, + /* mem offset minus 1 */ + tic6x_coding_mem_offset_minus_one, + /* non aligned mem offset minus 1 */ + tic6x_coding_mem_offset_minus_one_noscale, + tic6x_coding_rside } tic6x_coding_method; /* How to generate the value of a particular field. */ @@ -530,7 +624,7 @@ typedef struct unsigned short isa_variants; /* Flags for this instruction. */ - unsigned short flags; + unsigned int flags; /* Number of fixed fields, or fields with restricted value ranges, for this instruction. */ @@ -570,9 +664,15 @@ typedef enum CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), #define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ CONCAT4(tic6x_opcode_,name,_,e), +#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \ + CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), +#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ + CONCAT6(tic6x_opcode_,name,_,func_unit,_,e), #include "tic6x-opcode-table.h" #undef INSN #undef INSNE +#undef INSNU +#undef INSNUE tic6x_opcode_max } tic6x_opcode_id; |