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| author | Terry Guo <terry.guo@arm.com> | 2014-11-21 11:31:37 +0800 |
|---|---|---|
| committer | Terry Guo <terry.guo@arm.com> | 2014-11-21 11:36:06 +0800 |
| commit | a715796ba188e7ca9eac6e613439b63fe50a677d (patch) | |
| tree | 4dd6a5f47fddcb7f5690e03ee49b51986bc0ffd8 /include | |
| parent | 45e44d277a1b558bb77ea0a1962172a06be26594 (diff) | |
| download | gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.zip gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.tar.gz gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.tar.bz2 | |
Support ARM Cortex-M7
include/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro.
(FPU_VFP_V5D16): Likewise.
(FPU_VFP_V5_SP_D16): Likewise.
(FPU_ARCH_VFP_V5D16): Likewise.
(FPU_ARCH_VFP_V5_SP_D16): Likewise.
bfd/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5.
binutils/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5.
gas/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
(arm_cpus): Support cortex-m7.
(arm_fpus): Support fpv5-sp-d16 and fpv5-d16.
(do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S
register only target like FPv5-SP-D16.
(do_neon_cvttb_1): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vrint_1): Likewise.
(aeabi_set_public_attributes): Set proper FP arch for FPv5.
* doc/c-arm.texi: Document new cpu and fpu names for cortex-m7.
gas/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/armv7e-m+fpv5-d16.s: New.
* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.
ld/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
* ld-arm/attr-merge-vfp-5-sp.s: Likewise.
* ld-arm/attr-merge-vfp-5.s: Likewise.
* ld-arm/attr-merge-vfp-8.d: New test.
* ld-arm/attr-merge-vfp-8r.d: Likewise.
* ld-arm/attr-merge-vfp-9.d: Likewise.
* ld-arm/attr-merge-vfp-9r.d: Likewise.
* ld-arm/attr-merge-vfp-10.d: Likewise.
* ld-arm/attr-merge-vfp-10r.d: Likewise.
* ld-arm/attr-merge-vfp-11.d: Likewise.
* ld-arm/attr-merge-vfp-11r.d: Likewise.
* ld-arm/attr-merge-vfp-12.d: Likewise.
* ld-arm/attr-merge-vfp-12r.d: Likewise.
* ld-arm/attr-merge-vfp-13.d: Likewise.
* ld-arm/attr-merge-vfp-13r.d: Likewise.
* ld-arm/attr-merge-vfp-14.d: Likewise.
* ld-arm/attr-merge-vfp-14r.d: Likewise.
* ld-arm/arm-elf.exp: Run the new tests.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/arm.h | 9 |
2 files changed, 15 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index bcd9b28..31a7996 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2014-11-21 Terry Guo <terry.guo@arm.com> + + * opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro. + (FPU_VFP_V5D16): Likewise. + (FPU_VFP_V5_SP_D16): Likewise. + (FPU_ARCH_VFP_V5D16): Likewise. + (FPU_ARCH_VFP_V5_SP_D16): Likewise. + 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * bfdlink.h (struct bfd_link_info): Add bndplt. diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 6d4825a..00475e1 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -78,10 +78,11 @@ #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ -#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ +#define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ +#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, @@ -153,7 +154,9 @@ #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) -#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) +#define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8) +#define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) +#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD) #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ @@ -186,6 +189,8 @@ #define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) #define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) +#define FPU_ARCH_VFP_V5D16 ARM_FEATURE(0, FPU_VFP_V5D16) +#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE(0, FPU_VFP_V5_SP_D16) #define FPU_ARCH_NEON_VFP_V4 \ ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) |