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| author | Andrew Pinski <apinski@cavium.com> | 2011-11-29 20:28:55 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@cavium.com> | 2011-11-29 20:28:55 +0000 |
| commit | dd6a37e700ab12b5f5e89b747992324e74981872 (patch) | |
| tree | 85cfdc8abc67b5b005f7bbdeb123bf5730918ae4 /include | |
| parent | b3364cb9c21f33b0f0de633d10f6729134b9bd6f (diff) | |
| download | gdb-dd6a37e700ab12b5f5e89b747992324e74981872.zip gdb-dd6a37e700ab12b5f5e89b747992324e74981872.tar.gz gdb-dd6a37e700ab12b5f5e89b747992324e74981872.tar.bz2 | |
opcode/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/mips.h | 10 |
2 files changed, 17 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index dd4a977..bfd71e0 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2011-11-29 Andrew Pinski <apinski@cavium.com> + + * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. + (INSN_OCTEONP): New macro. + (CPU_OCTEONP): New macro. + (OPCODE_IS_MEMBER): Add Octeon+. + (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. + 2011-11-01 DJ Delorie <dj@redhat.com> * rl78.h: New file. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index a94860f..eb28d16 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -713,10 +713,11 @@ static const unsigned int mips_isa_table[] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0c20 +#define INSN_CHIP_MASK 0xc3ff0e20 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 +#define INSN_OCTEONP 0x00000200 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x3c00f010 @@ -823,6 +824,7 @@ static const unsigned int mips_isa_table[] = #define CPU_LOONGSON_2F 3002 #define CPU_LOONGSON_3A 3003 #define CPU_OCTEON 6501 +#define CPU_OCTEONP 6601 #define CPU_XLR 887682 /* decimal 'XLR' */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -859,6 +861,8 @@ static const unsigned int mips_isa_table[] = && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ || (cpu == CPU_OCTEON \ && ((insn)->membership & INSN_OCTEON) != 0) \ + || (cpu == CPU_OCTEONP \ + && ((insn)->membership & INSN_OCTEONP) != 0) \ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ || 0) /* Please keep this term for easier source merging. */ @@ -1065,6 +1069,10 @@ enum M_S_DOB, M_S_DAB, M_S_S, + M_SAA_AB, + M_SAA_OB, + M_SAAD_AB, + M_SAAD_OB, M_SC_AB, M_SC_OB, M_SCD_AB, |