diff options
| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:55:25 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:55:25 +0800 |
| commit | 9108bc33b1ca0b2e930c0cce5b1a0394e33e86be (patch) | |
| tree | adb7aaf17163d449da228c09b5f7c94b80e3163d /include | |
| parent | bd782c07b914f28fd927cec42eacd8adcf556dca (diff) | |
| download | gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.zip gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.tar.gz gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.tar.bz2 | |
[MIPS] Add Loongson 2K1000 proccessor support.
bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs264e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS264E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs264e to
bfd_mach_mips_gs464e extension.
binutils/
* NEWS: Mention Loongson 2K1000 proccessor support.
* readelf.c (get_machine_flags): Handle gs264e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
(mips_cpu_info_table): Add gs264e descriptors.
* doc/as.texi (march table): Add gs264e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
* opcode/mips.h (CPU_XXX): New CPU_GS264E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs264e and gs464e.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/elf/mips.h | 1 | ||||
| -rw-r--r-- | include/opcode/mips.h | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 623c954..6c19b1d 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. + * opcode/mips.h (CPU_XXX): New CPU_GS264E. + +2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. diff --git a/include/elf/mips.h b/include/elf/mips.h index e27b6af..3858ee3 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -301,6 +301,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_LS2F 0x00A10000 #define E_MIPS_MACH_GS464 0x00A20000 #define E_MIPS_MACH_GS464E 0x00A30000 +#define E_MIPS_MACH_GS264E 0x00A40000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 4ad65c9..fe8d16b 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1374,6 +1374,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_LOONGSON_2F 3002 #define CPU_GS464 3003 #define CPU_GS464E 3004 +#define CPU_GS264E 3005 #define CPU_OCTEON 6501 #define CPU_OCTEONP 6601 #define CPU_OCTEON2 6502 |