bfd:

	* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
	(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
	(BFD32_BACKENDS): Add elf32-tic6x.lo.
	(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
	* Makefile.in: Regenerate.
	* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
	(bfd_archures_list): Update.
	* config.bfd (tic6x-*-elf): New.
	* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
	New.
	* configure: Regenerate.
	* cpu-tic6x.c, elf32-tic6x.c: New.
	* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
	BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
	BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
	BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
	BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
	BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
	BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
	BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
	BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
	BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
	BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
	BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
	BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
	* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
	(_bfd_target_vector): Update.
	* bfd-in2.h, libbfd.h: Regenerate.

binutils:
	* MAINTAINERS: Add self as TI C6X maintainer.
	* NEWS: Add news entry for TI C6X support.
	* readelf.c: Include elf/tic6x.h.
	(guess_is_rela): Handle EM_TI_C6000.
	(dump_relocations): Likewise.
	(get_tic6x_dynamic_type): New.
	(get_dynamic_type): Call it.
	(get_machine_flags): Handle EF_C6000_REL.
	(get_osabi_name): Handle machine-specific values only for relevant
	machines.  Handle C6X values.
	(get_tic6x_segment_type): New.
	(get_segment_type): Call it.
	(get_tic6x_section_type_name): New.
	(get_section_type_name): Call it.
	(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
	EM_TI_C6000.

gas:
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
	(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
	* Makefile.in: Regenerate.
	* NEWS: Add news entry for TI C6X support.
	* app.c (do_scrub_chars): Handle "||^" for TI C6X.  Handle
	TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR.  Keep spaces in
	operands if TC_KEEP_OPERAND_SPACES.
	* configure.tgt (tic6x-*-*): New.
	* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
	TC_PREDICATE_END_CHAR): Define.
	* config/tc-tic6x.c, config/tc-tic6x.h: New.
	* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
	* doc/Makefile.in: Regenerate.
	* doc/all.texi (TIC6X): Define.
	* doc/as.texinfo: Add TI C6X documentation.  Include c-tic6x.texi.
	* doc/c-tic6x.texi: New.

gas/testsuite:
	* gas/tic6x: New directory and testcases.

include:
	* dis-asm.h (print_insn_tic6x): Declare.

include/elf:
	* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
	* tic6x.h: New.

include/opcode:
	* tic6x-control-registers.h, tic6x-insn-formats.h,
	tic6x-opcode-table.h, tic6x.h: New.

ld:
	* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
	eelf32_tic6x_le.o.
	(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
	* NEWS: Add news entry for TI C6X support.
	* configure.tgt (tic6x-*-*): New.
	* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.

ld/testsuite:
	* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
	* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
	* ld-tic6x: New directory and testcases.

opcodes:
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
	* Makefile.in: Regenerate.
	* configure.in (bfd_tic6x_arch): New.
	* configure: Regenerate.
	* disassemble.c (ARCH_tic6x): Define if ARCH_all.
	(disassembler): Handle TI C6X.
	* tic6x-dis.c: New.

10 files changed, 3561 insertions, 1 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 9eb59aa..584512d 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* dis-asm.h (print_insn_tic6x): Declare.
+
 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 
 	* symcat.h (CONCAT5, CONCAT6, XCONCAT5, XCONCAT6): Define.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 103f670..c4fb9f3 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -1,6 +1,6 @@
 /* Interface between the opcode library and its callers.
 
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -286,6 +286,7 @@ extern int print_insn_spu		(bfd_vma, disassemble_info *);
 extern int print_insn_tic30		(bfd_vma, disassemble_info *);
 extern int print_insn_tic4x		(bfd_vma, disassemble_info *);
 extern int print_insn_tic54x		(bfd_vma, disassemble_info *);
+extern int print_insn_tic6x		(bfd_vma, disassemble_info *);
 extern int print_insn_tic80		(bfd_vma, disassemble_info *);
 extern int print_insn_v850		(bfd_vma, disassemble_info *);
 extern int print_insn_vax		(bfd_vma, disassemble_info *);
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index e9aa748..52e1024 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
+	* tic6x.h: New.
+
 2010-03-05  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
 	* common.h (VER_FLG_*): Document.
diff --git a/include/elf/common.h b/include/elf/common.h
index 6bad0d9..8459b9f 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -75,6 +75,8 @@
 #define ELFOSABI_NSK	     14	/* Hewlett-Packard Non-Stop Kernel */
 #define ELFOSABI_AROS	     15	/* AROS */
 #define ELFOSABI_FENIXOS     16 /* FenixOS */
+#define ELFOSABI_C6000_ELFABI 64 /* Bare-metal TMS320C6000 */
+#define ELFOSABI_C6000_LINUX 65 /* Linux TMS320C6000 */
 #define ELFOSABI_ARM	     97	/* ARM */
 #define ELFOSABI_STANDALONE 255	/* Standalone (embedded) application */
 
diff --git a/include/elf/tic6x.h b/include/elf/tic6x.h
new file mode 100644
index 0000000..c4ec193
--- /dev/null
+++ b/include/elf/tic6x.h
@@ -0,0 +1,128 @@
+/* TI C6X ELF support for BFD.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_TIC6X_H
+#define _ELF_TIC6X_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_tic6x_reloc_type)
+  RELOC_NUMBER (R_C6000_NONE, 0)
+  RELOC_NUMBER (R_C6000_ABS32, 1)
+  RELOC_NUMBER (R_C6000_ABS16, 2)
+  RELOC_NUMBER (R_C6000_ABS8, 3)
+  RELOC_NUMBER (R_C6000_PCR_S21, 4)
+  RELOC_NUMBER (R_C6000_PCR_S12, 5)
+  RELOC_NUMBER (R_C6000_PCR_S10, 6)
+  RELOC_NUMBER (R_C6000_PCR_S7, 7)
+  RELOC_NUMBER (R_C6000_ABS_S16, 8)
+  RELOC_NUMBER (R_C6000_ABS_L16, 9)
+  RELOC_NUMBER (R_C6000_ABS_H16, 10)
+  RELOC_NUMBER (R_C6000_SBR_U15_B, 11)
+  RELOC_NUMBER (R_C6000_SBR_U15_H, 12)
+  RELOC_NUMBER (R_C6000_SBR_U15_W, 13)
+  RELOC_NUMBER (R_C6000_SBR_S16, 14)
+  RELOC_NUMBER (R_C6000_SBR_L16_B, 15)
+  RELOC_NUMBER (R_C6000_SBR_L16_H, 16)
+  RELOC_NUMBER (R_C6000_SBR_L16_W, 17)
+  RELOC_NUMBER (R_C6000_SBR_H16_B, 18)
+  RELOC_NUMBER (R_C6000_SBR_H16_H, 19)
+  RELOC_NUMBER (R_C6000_SBR_H16_W, 20)
+  RELOC_NUMBER (R_C6000_SBR_GOT_U15_W, 21)
+  RELOC_NUMBER (R_C6000_SBR_GOT_L16_W, 22)
+  RELOC_NUMBER (R_C6000_SBR_GOT_H16_W, 23)
+  RELOC_NUMBER (R_C6000_DSBT_INDEX, 24)
+  RELOC_NUMBER (R_C6000_PREL31, 25)
+  RELOC_NUMBER (R_C6000_COPY, 26)
+  RELOC_NUMBER (R_C6000_ALIGN, 253)
+  RELOC_NUMBER (R_C6000_FPHEAD, 254)
+  RELOC_NUMBER (R_C6000_NOCMP, 255)
+END_RELOC_NUMBERS (R_TIC6X_max)
+
+/* Processor-specific flags.  */
+
+/* File contains static relocation information.  */
+#define EF_C6000_REL		0x1
+
+/* Processor-specific section types.  */
+
+/* Unwind function table for stack unwinding.  */
+#define SHT_C6000_UNWIND	0x70000001
+
+/* DLL dynamic linking pre-emption map.  */
+#define SHT_C6000_PREEMPTMAP	0x70000002
+
+/* Object file compatibility attributes.  */
+#define SHT_C6000_ATTRIBUTES	0x70000003
+
+/* Intermediate code for link-time optimization.  */
+#define SHT_TI_ICODE		0x7F000000
+
+/* Symbolic cross reference information.  */
+#define SHT_TI_XREF		0x7F000001
+
+/* Reserved.  */
+#define SHT_TI_HANDLER		0x7F000002
+
+/* Compressed data for initializing C variables.  */
+#define SHT_TI_INITINFO		0x7F000003
+
+/* Extended program header attributes.  */
+#define SHT_TI_PHATTRS		0x7F000004
+
+/* Processor-specific segment types.  */
+
+/* Extended Segment Attributes.  */
+#define PT_C6000_PHATTR		0x70000000
+
+/* Processor-specific dynamic tags.  */
+
+/* Undocumented.  */
+#define DT_C6000_GSYM_OFFSET	0x6000000D
+
+/* Undocumented.  */
+#define DT_C6000_GSTR_OFFSET	0x6000000F
+
+/* Statically linked base address of data segment.  */
+#define DT_C6000_DSBT_BASE	0x70000000
+
+/* Number of entries in this module's DSBT.  */
+#define DT_C6000_DSBT_SIZE	0x70000001
+
+/* Undocumented.  */
+#define DT_C6000_PREEMPTMAP	0x70000002
+
+/* The hard-coded DSBT index for this module, if any.  */
+#define DT_C6000_DSBT_INDEX	0x70000003
+
+/* Extended program header attributes.  */
+
+/* Terminate a segment.  */
+#define PHA_NULL		0x0
+
+/* Segment's address bound to the final address.  */
+#define PHA_BOUND		0x1
+
+/* Segment cannot be further relocated.  */
+#define PHA_READONLY		0x2
+
+#endif /* _ELF_TIC6X_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 549d565..fb208d2 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-control-registers.h, tic6x-insn-formats.h,
+	tic6x-opcode-table.h, tic6x.h: New.
+
 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 
 	* mips.h: (LOONGSON2F_NOP_INSN): New macro.
diff --git a/include/opcode/tic6x-control-registers.h b/include/opcode/tic6x-control-registers.h
new file mode 100644
index 0000000..e237f06
--- /dev/null
+++ b/include/opcode/tic6x-control-registers.h
@@ -0,0 +1,54 @@
+/* TI C6X control register information.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the CTRL macro before including this file; it takes as
+   arguments the fields from tic6x_ctrl (defined in tic6x.h).  The
+   control register name is given as an identifier; the isa_variants
+   field without the leading TIC6X_INSN_; the rw field without the
+   leading tic6x_rw_.  */
+
+CTRL(amr, C62X, read_write, 0x0, 0x10)
+CTRL(csr, C62X, read_write, 0x1, 0x10)
+CTRL(dnum, C64XP, read, 0x11, 0x1f)
+CTRL(ecr, C64XP, write, 0x1d, 0x1f)
+CTRL(efr, C64XP, read, 0x1d, 0x1f)
+CTRL(fadcr, C67X, read_write, 0x12, 0x1f)
+CTRL(faucr, C67X, read_write, 0x13, 0x1f)
+CTRL(fmcr, C67X, read_write, 0x14, 0x1f)
+CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f)
+CTRL(gplya, C64XP, read_write, 0x16, 0x1f)
+CTRL(gplyb, C64XP, read_write, 0x17, 0x1f)
+CTRL(icr, C62X, write, 0x3, 0x10)
+CTRL(ier, C62X, read_write, 0x4, 0x10)
+CTRL(ierr, C64XP, read_write, 0x1f, 0x1f)
+CTRL(ifr, C62X, read, 0x2, 0x1d)
+CTRL(ilc, C64XP, read_write, 0xd, 0x1f)
+CTRL(irp, C62X, read_write, 0x6, 0x10)
+CTRL(isr, C62X, write, 0x2, 0x10)
+CTRL(istp, C62X, read_write, 0x5, 0x10)
+CTRL(itsr, C64XP, read_write, 0x1b, 0x1f)
+CTRL(nrp, C62X, read_write, 0x7, 0x10)
+CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f)
+CTRL(pce1, C62X, read, 0x10, 0xf)
+CTRL(rep, C64XP, read_write, 0xf, 0x1f)
+CTRL(rilc, C64XP, read_write, 0xe, 0x1f)
+CTRL(ssr, C64XP, read_write, 0x15, 0x1f)
+CTRL(tsch, C64XP, read, 0xb, 0x1f)
+CTRL(tscl, C64XP, read, 0xa, 0x1f)
+CTRL(tsr, C64XP, read_write, 0x1a, 0x1f)
diff --git a/include/opcode/tic6x-insn-formats.h b/include/opcode/tic6x-insn-formats.h
new file mode 100644
index 0000000..362dbb6
--- /dev/null
+++ b/include/opcode/tic6x-insn-formats.h
@@ -0,0 +1,198 @@
+/* TI C6X instruction format information.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the FMT macro before including this file; it takes a name
+   and the fields from tic6x_insn_format (defined in tic6x.h).  */
+
+#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) }
+#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
+#define CFLDS2(a, b) 5, { CFLDS, a, b }
+#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
+#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
+#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
+#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
+#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
+#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
+#define NFLDS FLD(p, 0, 1)
+#define NFLDS1(a) 2, { NFLDS, a }
+#define NFLDS2(a, b) 3, { NFLDS, a, b }
+#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
+#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
+#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
+#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
+
+/* These are in the order from SPRUFE8, appendices C-H.  */
+
+/* Appendix C 32-bit formats.  */
+
+FMT(d_1_or_2_src, 32, 0x40, 0x7c,
+    CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(d_load_store, 32, 0x4, 0xc,
+    CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
+	   FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
+	   FLD(srcdst, 23, 5)))
+/* The nonaligned loads and stores have the formats shown in the
+   individual instruction descriptions; the appendix is incorrect.  */
+FMT(d_load_nonaligned, 32, 0x124, 0x17c,
+    CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+	   FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
+FMT(d_store_nonaligned, 32, 0x174, 0x17c,
+    CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+	   FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
+FMT(d_load_store_long, 32, 0xc, 0xc,
+    CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+	   FLD(dst, 23, 5)))
+FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
+    NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+	   FLD(dst, 23, 5)))
+
+/* Appendix C 16-bit formats will go here.  */
+
+/* Appendix D 32-bit formats.  */
+
+FMT(l_1_or_2_src, 32, 0x18, 0x1c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
+    NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_unary, 32, 0x358, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+
+/* Appendix D 16-bit formats will go here.  */
+
+/* Appendix E 32-bit formats.  */
+
+FMT(m_compound, 32, 0x30, 0x83c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
+    NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+/* Contrary to SPRUFE8, this does have predicate fields.  */
+FMT(m_unary, 32, 0xf0, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+
+/* M-unit formats missing from Appendix E.  */
+FMT(m_mpy, 32, 0x0, 0x7c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* Appendix E 16-bit formats will go here.  */
+
+/* Appendix F 32-bit formats.  */
+
+FMT(s_1_or_2_src, 32, 0x20, 0x3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23 ,5)))
+FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
+    NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
+FMT(s_unary, 32, 0xf20, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
+    CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
+FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
+    NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
+FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
+FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
+FMT(s_branch, 32, 0x360, 0xf8feffc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
+FMT(s_mvk, 32, 0x28, 0x3c,
+    CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_field, 32, 0x8, 0x3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* S-unit formats missing from Appendix F.  */
+FMT(s_addk, 32, 0x50, 0x7c,
+    CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_addkpc, 32, 0x160, 0x1ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
+FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_bdec, 32, 0x1020, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+FMT(s_bpos, 32, 0x20, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+
+/* Appendix F 16-bit formats will go here.  */
+
+/* Appendix G 16-bit formats will go here.  */
+
+/* Appendix H 32-bit formats.  */
+
+FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
+/* Corrected relative to Appendix H.  */
+FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
+    NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
+
+/* No-unit formats missing from Appendix H (given the NOP and IDLE
+   correction).  */
+FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+/* Although formally covered by the loop buffer format, the fields in
+   that format are not useful for all such instructions and not all
+   instructions can be predicated.  */
+FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
+    NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
+FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
+    NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
+
+/* Appendix H 16-bit formats will go here.  */
+
+#undef FLD
+#undef CFLDS
+#undef CFLDS2
+#undef CFLDS3
+#undef CFLDS4
+#undef CFLDS5
+#undef CFLDS6
+#undef CFLDS7
+#undef CFLDS8
+#undef NFLDS
+#undef NFLDS1
+#undef NFLDS2
+#undef NFLDS3
+#undef NFLDS5
+#undef NFLDS6
+#undef NFLDS7
diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h
new file mode 100644
index 0000000..5bd8f17
--- /dev/null
+++ b/include/opcode/tic6x-opcode-table.h
@@ -0,0 +1,2549 @@
+/* TI C6X opcode table.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the INSN macro before including this file; it takes as
+   arguments the fields from tic6x_opcode (defined in tic6x.h).  The
+   name is given as an identifier; the subsequent four operands should
+   have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_"
+   and "TIC6X_INSN_", respectively, prepended to them by the macro
+   definition.  Also define INSNE, which has a second argument that
+   goes after tic6x_opcode_NAME_ to form the enumeration value for
+   this instruction, where the value otherwise formed from the name,
+   functional unit and format is ambiguous, but otherwise has the same
+   arguments as INSN.  */
+
+#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X
+#define tic6x_insn_format_nfu_s_branch_nop_cst	\
+  tic6x_insn_format_s_branch_nop_cst
+#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src
+#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) }
+#define FIX(id, val) RAN(id, val, val)
+#define FIX0() 0, { { 0, 0, 0 } }
+#define FIX1(a) 1, { a }
+#define FIX2(a, b) 2, { a, b }
+#define FIX3(a, b, c) 3, { a, b, c }
+#define FIX4(a, b, c, d) 4, { a, b, c, d }
+#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }
+#define OP1(a) 1, { a }
+#define OP2(a, b) 2, { a, b }
+#define OP3(a, b, c) 3, { a, b, c }
+#define OP4(a, b, c, d) 4, { a, b, c, d }
+#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 }
+#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 }
+#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 }
+#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 }
+#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 }
+#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 }
+#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 }
+#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 }
+#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 }
+#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 }
+#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 }
+#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 }
+#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }
+#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
+#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
+#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ENC(id, meth, op) {			\
+    CONCAT2(tic6x_field_,id),			\
+    CONCAT2(tic6x_coding_,meth),		\
+    op						\
+  }
+#define ENC0() 0, { { 0, 0, 0 } }
+#define ENC1(a) 1, { a }
+#define ENC2(a, b) 2, { a, b }
+#define ENC3(a, b, c) 3, { a, b, c }
+#define ENC4(a, b, c, d) 4, { a, b, c, d }
+#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e }
+#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f }
+#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g }
+
+INSN(abs, l, unary, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGL1, OWREGL1),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abs2, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abssp, s, unary, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x23)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x21)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x20), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x10)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x12)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xa)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xb)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, scst, 1), ENC(dst, reg, 2)))
+
+INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x30)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x32)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 3)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1),
+	  ENC(dst, reg, 2)))
+
+INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3c)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3d)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x34)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x36)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 5)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1),
+	  ENC(dst, reg, 2)))
+
+INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x38)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x3a)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 7)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1),
+	  ENC(dst, reg, 2)))
+
+INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREGD12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0,
+     FIX1(FIX(op, 0x72)),
+     OP3(ORREGD12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+
+INSN(addkpc, s, addkpc, 1cycle, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX1(FIX(s, 1)),
+     OP3(OLCST, OWREG1, OACST),
+     ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2)))
+
+INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0,
+     FIX1(FIX(op, 0x70)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x2b)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x29)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x65)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x6)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x7c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x6)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avg2, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x13)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avgu4, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x12)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, ORWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(bitc4, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1e)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(bitr, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1f)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(bnop, s, branch_nop_cst, branch, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(s, 0)),
+     OP2(OLCST, OACST),
+     ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, s, branch_nop_reg, branch, C64X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(s, 1)),
+     OP2(ORXREG1, OACST),
+     ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, ORREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(call, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(call, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(call, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(call, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(callnop, s, branch_nop_cst, branch, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 0)),
+     OP2(OLCST, OACST),
+     ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, s, branch_nop_reg, branch, C64X,
+     TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 1)),
+     OP2(ORXREG1, OACST),
+     ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(callp, s, call_imm_nop, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(z, 1)),
+     OP2(OLCST, OWRETREG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(callret, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(callret, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(callret, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(callret, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x3)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x3f)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x53)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x52)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x51)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x50), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x28)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x38)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x47)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x46)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x45)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x44), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x57)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x56)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x55)),
+      OP3(ORREGL1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x54), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+
+INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x29)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x39)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x4f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a
+   5-bit unsigned constant operand on C64X and above.  */
+INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+      FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x4d)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x57)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x56)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x55)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x54), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x47)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x46)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x45)),
+      OP3(ORREGL1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x44), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+
+INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x2a)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x3a)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x5f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+      FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x5d)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xa)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xb)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmtl, d, 1_or_2_src, load, ATOMIC,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)),
+     OP2(ORMEMDW, OWDREG5),
+     ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREGD1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREGD1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREGD1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREGD1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(deal, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(dint, nfu, dint, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xb)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0,
+      FIX1(FIX(op, 0xc)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0,
+      FIX1(FIX(op, 0xb)),
+      OP3(ORREG1, ORXREG1, OWREGD4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpn2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x7)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x7)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprsu2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpsu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x6)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x34)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x33)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x1)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x2f)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x0)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x2b)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x1f), FIX(x, 0)),
+     OP3(ORREG1, ORREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+	  ENC(dst, reg, 2)))
+
+/* This instruction can be predicated as usual; SPRUFE8 is incorrect
+   where it shows the "z" field as fixed to 1.  */
+INSN(gmpy4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP,
+     FIX2(FIX(s, 0), FIX(op, 0xf)),
+     OP0(),
+     ENC0())
+
+INSN(intdp, l, 1_or_2_src, intdp, C67X, 0,
+     FIX2(FIX(op, 0x39), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD45),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0,
+     FIX2(FIX(op, 0x3b), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD45),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x4a), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x49), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ldb, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 2), FIX(r, 0)),
+     OP2(ORMEMSB, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldb, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 2)),
+     OP2(ORMEMLB, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ldbu, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 1), FIX(r, 0)),
+     OP2(ORMEMSB, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldbu, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 1)),
+     OP2(ORMEMLB, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(lddw, d, load_store, load, C64X_AND_C67X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 6), FIX(r, 1)),
+     OP2(ORMEMSD, OWDREGD5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+
+INSN(ldh, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 4), FIX(r, 0)),
+     OP2(ORMEMSH, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldh, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 4)),
+     OP2(ORMEMLH, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ldhu, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 0), FIX(r, 0)),
+     OP2(ORMEMSH, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldhu, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 0)),
+     OP2(ORMEMLH, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ldndw, d, load_nonaligned, load, C64X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX0(),
+     OP2(ORMEMND, OWDREGD5),
+     ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0),
+	  ENC(sc, scaled, 0), ENC(dst, reg_shift, 1)))
+
+INSN(ldnw, d, load_store, load, C64X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX2(FIX(op, 3), FIX(r, 1)),
+     OP2(ORMEMSW, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+
+INSN(ldw, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 6), FIX(r, 0)),
+     OP2(ORMEMSW, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldw, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 6)),
+     OP2(ORMEMLW, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ll, d, 1_or_2_src, load, ATOMIC,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)),
+     OP2(ORMEMDW, OWDREG5),
+     ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x42)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x43)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x41)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x48)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x19)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x18)),
+      OP3(OACST, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x0e), FIX(x, 0)),
+     OP3(ORREGD1234, ORREGD1324, OWREGD910),
+     ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+	  ENC(dst, reg, 2)))
+
+INSN(mpyh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x01)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhi, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhir, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhl, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x09)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhlu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhslu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0b)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhsu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x07)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhuls, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0d)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhus, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0,
+      FIX1(FIX(op, 0x04)),
+      OP3(ORREG14, ORXREG14, OWREG9),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0,
+      FIX1(FIX(op, 0x06)),
+      OP3(OACST, ORXREG14, OWREG9),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0,
+      FIX1(FIX(op, 0x08)),
+      OP3(ORREG14, ORXREG14, OWREGD910),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0,
+      FIX1(FIX(op, 0x0c)),
+      OP3(OACST, ORXREG14, OWREGD910),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylhu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyli, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylir, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylshu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x13)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyluhs, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp, m, mpy, 4cycle, C67X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and
+   C67X+.  */
+INSN(mpyspdp, m, compound, mpyspdp, C67X, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREG12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREG1, ORXREG1, OWREGD45),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x1b)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(OACST, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1f)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x04)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x00)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0,
+      FIX1(FIX(op, 0x10)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0,
+      FIX1(FIX(op, 0x14)),
+      OP3(ORREG1, ORXREG1, OWREGD4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32su, m, mpy, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32u, m, compound, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32us, m, compound, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x19)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* "or" forms of "mv" are preferred over "add" forms when available
+   because "or" uses less power.  However, 40-bit moves are only
+   available through "add", and before C64X D-unit moves are only
+   available through "add" (without cross paths being available).  */
+INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x7e), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)),
+      OP2(ORREGL1, OWREGL1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x1a), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0),
+      FIX2(FIX(op, 0x12), FIX(src1, 0)),
+      OP2(ORREG1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x3), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+
+INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)),
+      OP2(ORCREG1, OWREG1),
+      ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1)))
+INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+      FIX2(FIX(s, 1), FIX(op, 0x0e)),
+      OP2(ORXREG1, OWCREG1),
+      ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1),
+	   ENC(dst, crlo, 1)))
+
+INSN(mvd, m, unary, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(h, 0)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(x, 0), FIX(op, 0x05)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x00), FIX(src2, 0)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1)))
+
+INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(h, 1)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1)))
+
+INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX1(FIX(h, 1)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX1(FIX(h, 0)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x16), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x06), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x24), FIX(src1, 0)),
+      OP2(ORREGL1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+
+INSN(nop, nfu, nop_idle, nop, C62X, 0,
+     FIX2(FIX(s, 0), RAN(op, 0, 8)),
+     OP1(OACST),
+     ENC1(ENC(op, ucst_minus_one, 0)))
+INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(s, 0), FIX(op, 0)),
+      OP0(),
+      ENC0())
+
+INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX2(FIX(op, 0x63), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)),
+      OP2(ORREGL1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0xf), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0xf)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1e)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x69)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x8)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1b)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x68)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX2(FIX(op, 0x3d), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ret, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(ret, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(ret, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(ret, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(retp, s, call_imm_nop, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX1(FIX(z, 1)),
+     OP2(OLCST, OWRETREG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(rint, nfu, rint, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0,
+      FIX1(FIX(op, 0x1d)),
+      OP3(ORXREG1, ORREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(ORXREG1, OACST, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX2(FIX(op, 0xb), FIX(z, 1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX2(FIX(op, 0x3e), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x31)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x12)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x30)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x20)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x3)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGL1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x2)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(set, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x3b)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(shfl, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x36)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x33)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x31), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x32)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x30), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x12)),
+      OP3(ORXREG1, OACST, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x61)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x37)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x35), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x36)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x34), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x18)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x62)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0xa)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x27)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x25), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x26)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x24), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x8)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x19)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sl, d, 1_or_2_src, store, ATOMIC,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)),
+     OP2(ORDREG1, OWMEMDW),
+     ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1)))
+
+INSN(smpy, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyhl, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0a)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpylh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x12)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpy2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x01)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct operand order for this
+   instruction.  */
+INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x19)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0,
+     FIX2(FIX(op, 0x02), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD12),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x0a), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP,
+      TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+      FIX1(FIX(s, 0)),
+      OP2(OACST, OACST),
+      ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1)))
+INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP,
+      TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO,
+      FIX2(FIX(s, 0), FIX(fstgfcyc, 0)),
+      OP0(),
+      ENC0())
+
+INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(sploop, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX2(FIX(s, 0), FIX(op, 0x8)),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+
+INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX2(FIX(s, 0), FIX(op, 0x9)),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+
+INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x0b), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x23)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x22)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sshvl, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORXREG1, ORREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(sshvr, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP3(ORXREG1, ORREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x0f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x1f)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x2c)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x64)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(stb, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 3), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSB),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(stb, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 3)),
+     OP2(ORDREG1, OWMEMLB),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1),
+	  ENC(dst, reg, 0)))
+
+INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 4), FIX(r, 1)),
+     OP2(ORDREGD1, OWMEMSD),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+
+INSN(sth, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 5), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSH),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(sth, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 5)),
+     OP2(ORDREG1, OWMEMLH),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1),
+	  ENC(dst, reg, 0)))
+
+INSN(stndw, d, store_nonaligned, store, C64X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX0(),
+     OP2(ORDREGD1, OWMEMND),
+     ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1),
+	  ENC(sc, scaled, 1), ENC(src, reg_shift, 0)))
+
+INSN(stnw, d, load_store, store, C64X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX2(FIX(op, 5), FIX(r, 1)),
+     OP2(ORDREG1, OWMEMSW),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+
+INSN(stw, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 7), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSW),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(stw, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 7)),
+     OP2(ORDREG1, OWMEMLW),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1),
+	  ENC(dst, reg, 0)))
+
+INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x07)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x17)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x27)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x37)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x06)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x24)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x20), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x17)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x16)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction; this instruction can be predicated.  */
+INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x5)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x6)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x11)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xc)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x31)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x33)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5a)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x35)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x37)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x39)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3b)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x4b)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x19)),
+      OP3(ORREGD12, ORXREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x1d)),
+      OP3(ORXREGD12, ORREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+      TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x73)),
+      OP3(ORREGD12, ORXREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+      TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x77)),
+      OP3(ORXREGD12, ORREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x11)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x15)),
+      OP3(ORXREG1, ORREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+      TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x71)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+      TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x75)),
+      OP3(ORXREG1, ORREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x2f)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x3f)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x04)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x66)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x1b), FIX(x, 0)),
+     OP2(ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x10), FIX(x, 0)),
+     OP2(ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(swap4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(swe, nfu, swe, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(swenr, nfu, swenr, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(unpkhu4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(unpkhu4, s, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(unpklu4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(unpklu4, s, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0xe)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0xf)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1b)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xpnd2, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x19)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(xpnd4, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x18)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX2(FIX(h, 0), FIX(cst, 0)),
+     OP1(OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSN(zero, l, unary, 1cycle, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+     FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)),
+     OP1(OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX2(FIX(op, 0x07), FIX(x, 0)),
+      OP1(OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x27), FIX(x, 0)),
+      OP1(OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)),
+      OP1(OWREG1),
+      ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x11)),
+      OP1(OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+
+#undef TIC6X_INSN_C64X_AND_C67X
+#undef tic6x_insn_format_nfu_s_branch_nop_cst
+#undef tic6x_insn_format_s_l_1_or_2_src
+#undef RAN
+#undef FIX
+#undef FIX0
+#undef FIX1
+#undef FIX2
+#undef FIX3
+#undef FIX4
+#undef OP0
+#undef OP1
+#undef OP2
+#undef OP3
+#undef OP4
+#undef OACST
+#undef OLCST
+#undef OFULIST
+#undef ORIRP1
+#undef ORNRP1
+#undef OWREG1
+#undef OWRETREG1
+#undef ORREG1
+#undef ORDREG1
+#undef ORWREG1
+#undef ORAREG1
+#undef ORXREG1
+#undef ORREG12
+#undef ORREG14
+#undef ORXREG14
+#undef OWREG2
+#undef OWREG4
+#undef OWREG9
+#undef OWDREG5
+#undef OWREGL1
+#undef ORREGL1
+#undef OWREGD1
+#undef OWREGD12
+#undef OWREGD4
+#undef ORREGD1
+#undef OWREGD45
+#undef OWREGD67
+#undef ORDREGD1
+#undef OWDREGD5
+#undef ORREGD12
+#undef ORXREGD12
+#undef ORREGD1234
+#undef ORREGD1324
+#undef OWREGD910
+#undef ORCREG1
+#undef OWCREG1
+#undef ORMEMDW
+#undef OWMEMDW
+#undef ORMEMSB
+#undef OWMEMSB
+#undef ORMEMLB
+#undef OWMEMLB
+#undef ORMEMSH
+#undef OWMEMSH
+#undef ORMEMLH
+#undef OWMEMLH
+#undef ORMEMSW
+#undef OWMEMSW
+#undef ORMEMLW
+#undef OWMEMLW
+#undef ORMEMSD
+#undef OWMEMSD
+#undef ORMEMND
+#undef OWMEMND
+#undef ENC
+#undef ENC0
+#undef ENC1
+#undef ENC2
+#undef ENC3
+#undef ENC4
+#undef ENC5
+#undef ENC6
+#undef ENC7
diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h
new file mode 100644
index 0000000..ab2f2e9
--- /dev/null
+++ b/include/opcode/tic6x.h
@@ -0,0 +1,614 @@
+/* TI C6X opcode information.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef OPCODE_TIC6X_H
+#define OPCODE_TIC6X_H
+
+#include "bfd.h"
+#include "symcat.h"
+
+/* A field in an instruction format.  The names are based on those
+   used in the architecture manuals.  */
+typedef enum
+  {
+    tic6x_field_baseR,
+    tic6x_field_creg,
+    tic6x_field_cst,
+    tic6x_field_csta,
+    tic6x_field_cstb,
+    tic6x_field_dst,
+    tic6x_field_fstgfcyc,
+    tic6x_field_h,
+    tic6x_field_mask,
+    tic6x_field_mode,
+    tic6x_field_offsetR,
+    tic6x_field_op,
+    tic6x_field_p,
+    tic6x_field_r,
+    tic6x_field_s,
+    tic6x_field_sc,
+    tic6x_field_src,
+    tic6x_field_src1,
+    tic6x_field_src2,
+    tic6x_field_srcdst,
+    tic6x_field_x,
+    tic6x_field_y,
+    tic6x_field_z
+  } tic6x_insn_field_id;
+
+typedef struct
+{
+  /* The name used to reference the field.  */
+  tic6x_insn_field_id field_id;
+
+  /* The least-significant bit position in the field.  */
+  unsigned short low_pos;
+
+  /* The number of bits in the field.  */
+  unsigned short width;
+} tic6x_insn_field;
+
+/* Maximum number of variable fields in an instruction format.  */
+#define TIC6X_MAX_INSN_FIELDS 11
+
+/* A particular instruction format.  */
+typedef struct
+{
+  /* How many bits in the instruction.  */
+  unsigned int num_bits;
+
+  /* Constant bits in the instruction.  */
+  unsigned int cst_bits;
+
+  /* Mask matching those bits.  */
+  unsigned int mask;
+
+  /* The number of instruction fields.  */
+  unsigned int num_fields;
+
+  /* Descriptions of instruction fields.  */
+  tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
+} tic6x_insn_format;
+
+/* An index into the table of instruction formats.  */
+typedef enum
+  {
+#define FMT(name, num_bits, cst_bits, mask, fields)	\
+  CONCAT2(tic6x_insn_format_, name),
+#include "tic6x-insn-formats.h"
+#undef FMT
+    tic6x_insn_format_max
+  } tic6x_insn_format_id;
+
+/* The table itself.  */
+extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
+
+/* If instruction format FMT has a field FIELD, return a pointer to
+   the description of that field; otherwise return NULL.  */
+
+const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
+					      tic6x_insn_field_id field);
+
+/* Description of a field (in an instruction format) whose value is
+   fixed, or constrained to be in a particular range, in a particular
+   opcode.  */
+typedef struct
+{
+  /* The name of the field.  */
+  tic6x_insn_field_id field_id;
+
+  /* The least value of the field in this instruction.  */
+  unsigned int min_val;
+
+  /* The greatest value of the field in this instruction.  */
+  unsigned int max_val;
+} tic6x_fixed_field;
+
+/* Bit-masks for defining instructions present on some subset of
+   processors; each indicates an instruction present on that processor
+   and those that are supersets of it.  The options passed to the
+   assembler determine a bit-mask ANDed with the bit-mask indicating
+   when the instruction was added to determine whether the instruction
+   is enabled.  */
+#define TIC6X_INSN_C62X		0x0001
+#define TIC6X_INSN_C64X		0x0002
+#define TIC6X_INSN_C64XP	0x0004
+#define TIC6X_INSN_C67X		0x0008
+#define TIC6X_INSN_C67XP	0x0010
+#define TIC6X_INSN_C674X	0x0020
+#define TIC6X_INSN_ATOMIC	0x0040
+
+/* Flags with further information about an opcode table entry.  */
+
+/* Only used by the assembler, not the disassembler.  */
+#define TIC6X_FLAG_MACRO	0x0001
+
+/* Must be first in its execute packet.  */
+#define TIC6X_FLAG_FIRST	0x0002
+
+/* Multi-cycle NOP (not used for the NOP n instruction itself, which
+   is only a multicycle NOP if n > 1).  */
+#define TIC6X_FLAG_MCNOP	0x0004
+
+/* Cannot be in parallel with a multi-cycle NOP.  */
+#define TIC6X_FLAG_NO_MCNOP	0x0008
+
+/* Load instruction.  */
+#define TIC6X_FLAG_LOAD		0x0010
+
+/* Store instruction.  */
+#define TIC6X_FLAG_STORE	0x0020
+
+/* Unaligned memory operation.  */
+#define TIC6X_FLAG_UNALIGNED	0x0040
+
+/* Only on side B.  */
+#define TIC6X_FLAG_SIDE_B_ONLY	0x0080
+
+/* Only on data path T2.  */
+#define TIC6X_FLAG_SIDE_T2_ONLY	0x0100
+
+/* Does not support cross paths.  */
+#define TIC6X_FLAG_NO_CROSS	0x0200
+
+/* Annotate this branch instruction as a call.  */
+#define TIC6X_FLAG_CALL		0x0400
+
+/* Annotate this branch instruction as a return.  */
+#define TIC6X_FLAG_RETURN	0x0800
+
+/* This instruction starts a software pipelined loop.  */
+#define TIC6X_FLAG_SPLOOP	0x1000
+
+/* This instruction ends a software pipelined loop.  */
+#define TIC6X_FLAG_SPKERNEL	0x2000
+
+/* This instruction takes a list of functional units as parameters;
+   although described as having one parameter, the number may be 0 to
+   8.  */
+#define TIC6X_FLAG_SPMASK	0x4000
+
+/* When more than one opcode matches the assembly source, prefer the
+   one with the highest value for this bit-field.  If two opcode table
+   entries can match the same syntactic form, they must have different
+   values here.  */
+#define TIC6X_PREFER_VAL(n)	(((n) & 0x8000) >> 15)
+#define TIC6X_FLAG_PREFER(n)	((n) << 15)
+#define TIC6X_NUM_PREFER	2
+
+/* Maximum number of fixed fields for a particular opcode.  */
+#define TIC6X_MAX_FIXED_FIELDS 4
+
+/* Maximum number of operands in the opcode table for a particular
+   opcode.  */
+#define TIC6X_MAX_OPERANDS 4
+
+/* Maximum number of operands in the source code for a particular
+   opcode (different from the number in the opcode table for SPMASK
+   and SPMASKR).  */
+#define TIC6X_MAX_SOURCE_OPERANDS 8
+
+/* Maximum number of variable fields for a particular opcode.  */
+#define TIC6X_MAX_VAR_FIELDS 7
+
+/* Which functional units an opcode uses.  This only describes the
+   basic choice of D, L, M, S or no functional unit; other fields are
+   used to describe further restrictions (instructions only operating
+   on one side), use of cross paths and load/store instructions using
+   one side for the address and the other side for the source or
+   destination register.  */
+typedef enum
+  {
+    tic6x_func_unit_d,
+    tic6x_func_unit_l,
+    tic6x_func_unit_m,
+    tic6x_func_unit_s,
+    tic6x_func_unit_nfu
+  } tic6x_func_unit_base;
+
+/* Possible forms of source operand.  */
+typedef enum
+  {
+    /* An assembly-time constant.  */
+    tic6x_operand_asm_const,
+    /* A link-time constant.  */
+    tic6x_operand_link_const,
+    /* A register, from the same side as the functional unit
+       selected.  */
+    tic6x_operand_reg,
+    /* A register, that is from the other side if a cross path is
+       used.  */
+    tic6x_operand_xreg,
+    /* A register, that is from the side of the data path
+       selected.  */
+    tic6x_operand_dreg,
+    /* An address register usable with 15-bit offsets (B14 or B15).
+       This is from the same side as the functional unit if a cross
+       path is not used, and the other side if a cross path is
+       used.  */
+    tic6x_operand_areg,
+    /* A return address register (A3 or B3), from the same side as the
+       functional unit selected.  */
+    tic6x_operand_retreg,
+    /* A register pair, from the same side as the functional unit
+       selected.  */
+    tic6x_operand_regpair,
+    /* A register pair, that is from the other side if a cross path is
+       used.  */
+    tic6x_operand_xregpair,
+    /* A register pair, from the side of the data path selected.  */
+    tic6x_operand_dregpair,
+    /* The literal string "irp" (case-insensitive).  */
+    tic6x_operand_irp,
+    /* The literal string "nrp" (case-insensitive).  */
+    tic6x_operand_nrp,
+    /* A control register.  */
+    tic6x_operand_ctrl,
+    /* A memory reference (base and offset registers from the side of
+       the functional unit selected), using either unsigned 5-bit
+       constant or register offset, if any offset; register offsets
+       cannot use unscaled () syntax.  */
+    tic6x_operand_mem_short,
+    /* A memory reference (base and offset registers from the side of
+       the functional unit selected), using either unsigned 5-bit
+       constant or register offset, if any offset; register offsets
+       can use unscaled () syntax (for LDNDW and STNDW).  */
+    tic6x_operand_mem_ndw,
+    /* A memory reference using 15-bit link-time constant offset
+       relative to B14 or B15.  */
+    tic6x_operand_mem_long,
+    /* A memory reference that only dereferences a register with no
+       further adjustments (*REG), that register being from the side
+       of the functional unit selected.  */
+    tic6x_operand_mem_deref,
+    /* A functional unit name or a list thereof (for SPMASK and
+       SPMASKR).  */
+    tic6x_operand_func_unit
+  } tic6x_operand_form;
+
+/* Whether something is, or can be, read or written.  */
+typedef enum
+  {
+    tic6x_rw_none,
+    tic6x_rw_read,
+    tic6x_rw_write,
+    tic6x_rw_read_write
+  } tic6x_rw;
+
+/* Description of a source operand and how it is used.  */
+typedef struct
+{
+  /* The syntactic form of the operand.  */
+  tic6x_operand_form form;
+
+  /* For non-constant operands, the size in bytes (1, 2, 4, 5 or
+     8).  Ignored for constant operands.  */
+  unsigned int size;
+
+  /* Whether the operand is read, written or both.  In addition to the
+     operations described here, address registers are read on cycle 1
+     regardless of when the memory operand is read or written, and may
+     be modified as described by the addressing mode, and control
+     registers may be implicitly read by some instructions.  There are
+     also some special cases not fully described by this
+     structure.
+
+     - For mpydp, the low part of src2 is read on cycles 1 and 3 but
+       not 2, and the high part on cycles 2 and 4 but not 3.
+
+     - The swap2 pseudo-operation maps to packlh2, reading the first
+       operand of swap2 twice.  */
+  tic6x_rw rw;
+
+  /* The first and last cycles (1 for E1, etc.) at which the operand,
+     or the low part for two-register operands, is read or
+     written.  */
+  unsigned short low_first;
+  unsigned short low_last;
+
+  /* Likewise, for the high part.  */
+  unsigned short high_first;
+  unsigned short high_last;
+} tic6x_operand_info;
+
+/* Ways of converting an operand or functional unit specifier to a
+   field value.  */
+typedef enum
+  {
+    /* Store an unsigned assembly-time constant (which must fit) in
+       the field.  */
+    tic6x_coding_ucst,
+    /* Store a signed constant (which must fit) in the field.  This
+       may be used both for assembly-time constants and for link-time
+       constants.  */
+    tic6x_coding_scst,
+    /* Subtract one from an unsigned assembly-time constant (which
+       must be strictly positive before the subtraction) and store the
+       value (which must fit) in the field.  */
+    tic6x_coding_ucst_minus_one,
+    /* Negate a signed assembly-time constant, and store the result of
+       negation (which must fit) in the field.  Used only for
+       pseudo-operations.  */
+    tic6x_coding_scst_negate,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in bytes, in the field.  For expression operands,
+       assembly-time constants are encoded as-is.  For memory
+       reference operands, the offset is encoded as-is if [] syntax is
+       used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_byte,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in half-words, in the field.  For expression
+       operands, assembly-time constants are encoded as-is.  For
+       memory reference operands, the offset is encoded as-is if []
+       syntax is used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_half,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in words, in the field.  For expression operands,
+       assembly-time constants are encoded as-is.  For memory
+       reference operands, the offset is encoded as-is if [] syntax is
+       used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_word,
+    /* Store the low 16 bits of a link-time constant in the field;
+       considered unsigned for disassembly.  */
+    tic6x_coding_lcst_low16,
+    /* Store the high 16 bits of a link-time constant in the field;
+       considered unsigned for disassembly.  */
+    tic6x_coding_lcst_high16,
+    /* Store a signed PC-relative value (address of label minus
+       address of fetch packet containing the current instruction,
+       counted in words) in the field.  */
+    tic6x_coding_pcrel,
+    /* Likewise, but counting in half-words if in a header-based fetch
+       packet.  */
+    tic6x_coding_pcrel_half,
+    /* Encode the register number (even number for a register pair) in
+       the field.  When applied to a memory reference, encode the base
+       register.  */
+    tic6x_coding_reg,
+    /* Store 0 for register B14, 1 for register B15.  When applied to
+       a memory reference, encode the base register.  */
+    tic6x_coding_areg,
+    /* Store the low part of a control register address.  */
+    tic6x_coding_crlo,
+    /* Store the high part of a control register address.  */
+    tic6x_coding_crhi,
+    /* Encode the even register number for a register pair, shifted
+       right by one bit.  */
+    tic6x_coding_reg_shift,
+    /* Store either the offset register or the 5-bit unsigned offset
+       for a memory reference.  If an offset uses the unscaled ()
+       form, which is only permitted with constants, it is scaled
+       according to the access size of the operand before being
+       stored.  */
+    tic6x_coding_mem_offset,
+    /* Store either the offset register or the 5-bit unsigned offset
+       for a memory reference, but with no scaling applied to the
+       offset (for nonaligned doubleword operations).  */
+    tic6x_coding_mem_offset_noscale,
+    /* Store the addressing mode for a memory reference.  */
+    tic6x_coding_mem_mode,
+    /* Store whether a memory reference is scaled.  */
+    tic6x_coding_scaled,
+    /* Store the stage in an SPKERNEL instruction in the upper part of
+       the field.  */
+    tic6x_coding_fstg,
+    /* Store the cycle in an SPKERNEL instruction in the lower part of
+       the field.  */
+    tic6x_coding_fcyc,
+    /* Store the mask bits for functional units in the field in an
+       SPMASK or SPMASKR instruction.  */
+    tic6x_coding_spmask,
+    /* Store the number of a register that is unused, or minimally
+       used, in this execute packet.  The number must be the same for
+       all uses of this coding in a single instruction, but may be
+       different for different instructions in the execute packet.
+       This is for the "zero" pseudo-operation.  This is not safe when
+       reads may occur from instructions in previous execute packets;
+       in such cases the programmer or compiler should use explicit
+       "sub" instructions for those cases of "zero" that cannot be
+       implemented as "mvk" for the processor specified.  */
+    tic6x_coding_reg_unused,
+    /* Store 1 if the functional unit used is on side B, 0 for side
+       A.  */
+    tic6x_coding_fu,
+    /* Store 1 if the data path used (source register for store,
+       destination for load) is on side B, 0 for side A.  */
+    tic6x_coding_data_fu,
+    /* Store 1 if the cross path is being used, 0 otherwise.  */
+    tic6x_coding_xpath
+  } tic6x_coding_method;
+
+/* How to generate the value of a particular field.  */
+typedef struct
+{
+  /* The name of the field.  */
+  tic6x_insn_field_id field_id;
+
+  /* How it is encoded.  */
+  tic6x_coding_method coding_method;
+
+  /* Source operand number, if any.  */
+  unsigned int operand_num;
+} tic6x_coding_field;
+
+/* Types of instruction for pipeline purposes.  The type determines
+   functional unit and cross path latency (when the same functional
+   unit can be used by other instructions, when the same cross path
+   can be used by other instructions).  */
+typedef enum
+  {
+    tic6x_pipeline_nop,
+    tic6x_pipeline_1cycle,
+    tic6x_pipeline_1616_m,
+    tic6x_pipeline_store,
+    tic6x_pipeline_mul_ext,
+    tic6x_pipeline_load,
+    tic6x_pipeline_branch,
+    tic6x_pipeline_2cycle_dp,
+    tic6x_pipeline_4cycle,
+    tic6x_pipeline_intdp,
+    tic6x_pipeline_dpcmp,
+    tic6x_pipeline_addsubdp,
+    tic6x_pipeline_mpyi,
+    tic6x_pipeline_mpyid,
+    tic6x_pipeline_mpydp,
+    tic6x_pipeline_mpyspdp,
+    tic6x_pipeline_mpysp2dp
+  } tic6x_pipeline_type;
+
+/* Description of a control register.  */
+typedef struct
+{
+  /* The name of the register.  */
+  const char *name;
+
+  /* Which ISA variants include this control register.  */
+  unsigned short isa_variants;
+
+  /* Whether it can be read, written or both (in supervisor mode).
+     Some registers use the same address, but different names, for
+     reading and writing.  */
+  tic6x_rw rw;
+
+  /* crlo value for this register.  */
+  unsigned int crlo;
+
+  /* Mask that, ANDed with the crhi value in the instruction, must be
+     0.  0 is always generated when generating code.  */
+  unsigned int crhi_mask;
+} tic6x_ctrl;
+
+/* An index into the table of control registers.  */
+typedef enum
+  {
+#define CTRL(name, isa, rw, crlo, crhi_mask)	\
+    CONCAT2(tic6x_ctrl_,name),
+#include "tic6x-control-registers.h"
+#undef CTRL
+    tic6x_ctrl_max
+  } tic6x_ctrl_id;
+
+/* The table itself.  */
+extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
+
+/* An entry in the opcode table.  */
+typedef struct
+{
+  /* The name of the instruction.  */
+  const char *name;
+
+  /* Functional unit used by this instruction (basic information).  */
+  tic6x_func_unit_base func_unit;
+
+  /* The format of this instruction.  */
+  tic6x_insn_format_id format;
+
+  /* The pipeline type of this instruction.  */
+  tic6x_pipeline_type type;
+
+  /* Which ISA variants include this instruction.  */
+  unsigned short isa_variants;
+
+  /* Flags for this instruction.  */
+  unsigned short flags;
+
+  /* Number of fixed fields, or fields with restricted value ranges,
+     for this instruction.  */
+  unsigned int num_fixed_fields;
+
+  /* Values of fields fixed for this instruction.  */
+  tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
+
+  /* The number of operands in the source form of this
+     instruction.  */
+  unsigned int num_operands;
+
+  /* Information about individual operands.  */
+  tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
+
+  /* The number of variable fields for this instruction with encoding
+     instructions explicitly given.  */
+  unsigned int num_variable_fields;
+
+  /* How fields (other than ones with fixed value) are computed from
+     the source operands and functional unit specifiers.  In addition
+     to fields specified here:
+
+     - creg, if present, is set from the predicate, along with z which
+       must be present if creg is present.
+
+     - p, if present (on all non-compact instructions), is set from
+       the parallel bars.
+  */
+  tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
+} tic6x_opcode;
+
+/* An index into the table of opcodes.  */
+typedef enum
+  {
+#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
+#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT4(tic6x_opcode_,name,_,e),
+#include "tic6x-opcode-table.h"
+#undef INSN
+#undef INSNE
+    tic6x_opcode_max
+  } tic6x_opcode_id;
+
+/* The table itself.  */
+extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
+
+/* A linked list of opcodes.  */
+typedef struct tic6x_opcode_list_tag
+{
+  tic6x_opcode_id id;
+  struct tic6x_opcode_list_tag *next;
+} tic6x_opcode_list;
+
+/* The information from a fetch packet header.  */
+typedef struct
+{
+  /* The header itself.  */
+  unsigned int header;
+
+  /* Whether each word uses compact instructions.  */
+  bfd_boolean word_compact[7];
+
+  /* Whether loads are protected.  */
+  bfd_boolean prot;
+
+  /* Whether instructions use the high register set.  */
+  bfd_boolean rs;
+
+  /* Data size.  */
+  unsigned int dsz;
+
+  /* Whether compact instructions in the S unit are decoded as
+     branches.  */
+  bfd_boolean br;
+
+  /* Whether compact instructions saturate.  */
+  bfd_boolean sat;
+
+  /* P-bits.  */
+  bfd_boolean p_bits[14];
+} tic6x_fetch_packet_header;
+
+#endif /* OPCODE_TIC6X_H */