[ARM] Remove ARMv6S-M special casing

=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.

=== Motivation ===

Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.

However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.

=== Patch description ===

The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.

The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.

2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_v6m): Delete.
	(arm_ext_v7m): Delete.
	(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
	profile.
	(arm_arch_v6m_only): Delete.
	(do_t_swi): Remove special case for ARMv6S-M.
	(md_assemble): Display error message previously in do_t_swi when
	SVC is not available.
	(insns): Guard swi and svc by arm_ext_os for Thumb mode.
	(aeabi_set_public_attributes): Remove special case for ARMv6S-M.

include/
	* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
	(ARM_AEXT_V4T): Likewise.
	(ARM_AEXT_V5TxM): Likewise.
	(ARM_AEXT_V5T): Likewise.
	(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.

2 files changed, 15 insertions, 5 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index d8730de..ec910a3 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,11 @@
+2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
+	(ARM_AEXT_V4T): Likewise.
+	(ARM_AEXT_V5TxM): Likewise.
+	(ARM_AEXT_V5T): Likewise.
+	(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
+
 2017-06-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* bfdlink.h (bfd_link_info): Add shstk.
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 5691a85..62683a3 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -106,12 +106,14 @@
 #define ARM_AEXT_V3M	(ARM_AEXT_V3	| ARM_EXT_V3M)
 #define ARM_AEXT_V4xM	(ARM_AEXT_V3	| ARM_EXT_V4)
 #define ARM_AEXT_V4	(ARM_AEXT_V3M	| ARM_EXT_V4)
-#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T)
-#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T)
+#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T | ARM_EXT_OS)
+#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T | ARM_EXT_OS)
 #define ARM_AEXT_V5xM	(ARM_AEXT_V4xM	| ARM_EXT_V5)
 #define ARM_AEXT_V5	(ARM_AEXT_V4	| ARM_EXT_V5)
-#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
-#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
+#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T \
+			 | ARM_EXT_OS)
+#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T \
+			 | ARM_EXT_OS)
 #define ARM_AEXT_V5TExP	(ARM_AEXT_V5T	| ARM_EXT_V5ExP)
 #define ARM_AEXT_V5TE	(ARM_AEXT_V5TExP | ARM_EXT_V5E)
 #define ARM_AEXT_V5TEJ	(ARM_AEXT_V5TE	| ARM_EXT_V5J)
@@ -136,7 +138,7 @@
 #define ARM_AEXT_V6M_ONLY \
   ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
 #define ARM_AEXT_V6M \
-  ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
+  ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM | ARM_EXT_OS))
 #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
 #define ARM_AEXT_V7M \
   ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \