This commit was manufactured by cvs2svn to create branch 'gdb_6_4-branch'.gdb_6_4-2005-11-01-branchpoint

Sprout from gdb-csl-arm-20051020-branch 2005-10-20 00:09:02 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb-csl-'
Cherrypick from master 2005-11-01 22:57:23 UTC Alan Modra <amodra@gmail.com> '	PR ld/1775':
    ChangeLog
    Makefile.def
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    bfd/ChangeLog
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    include/ChangeLog
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    include/opcode/ChangeLog
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    sim/testsuite/sim/sh64/media/fldxp.cgs
    sim/testsuite/sim/sh64/media/fldxs.cgs
    sim/testsuite/sim/sh64/media/floatld.cgs
    sim/testsuite/sim/sh64/media/floatls.cgs
    sim/testsuite/sim/sh64/media/floatqd.cgs
    sim/testsuite/sim/sh64/media/floatqs.cgs
    sim/testsuite/sim/sh64/media/fmacs.cgs
    sim/testsuite/sim/sh64/media/fmovd.cgs
    sim/testsuite/sim/sh64/media/fmovdq.cgs
    sim/testsuite/sim/sh64/media/fmovls.cgs
    sim/testsuite/sim/sh64/media/fmovqd.cgs
    sim/testsuite/sim/sh64/media/fmovs.cgs
    sim/testsuite/sim/sh64/media/fmovsl.cgs
    sim/testsuite/sim/sh64/media/fmuld.cgs
    sim/testsuite/sim/sh64/media/fmuls.cgs
    sim/testsuite/sim/sh64/media/fnegd.cgs
    sim/testsuite/sim/sh64/media/fnegs.cgs
    sim/testsuite/sim/sh64/media/fputscr.cgs
    sim/testsuite/sim/sh64/media/fsqrtd.cgs
    sim/testsuite/sim/sh64/media/fsqrts.cgs
    sim/testsuite/sim/sh64/media/fstd.cgs
    sim/testsuite/sim/sh64/media/fstp.cgs
    sim/testsuite/sim/sh64/media/fsts.cgs
    sim/testsuite/sim/sh64/media/fstxd.cgs
    sim/testsuite/sim/sh64/media/fstxp.cgs
    sim/testsuite/sim/sh64/media/fstxs.cgs
    sim/testsuite/sim/sh64/media/fsubd.cgs
    sim/testsuite/sim/sh64/media/fsubs.cgs
    sim/testsuite/sim/sh64/media/ftrcdl.cgs
    sim/testsuite/sim/sh64/media/ftrcdq.cgs
    sim/testsuite/sim/sh64/media/ftrcsl.cgs
    sim/testsuite/sim/sh64/media/ftrcsq.cgs
    sim/testsuite/sim/sh64/media/ftrvs.cgs
    sim/testsuite/sim/sh64/media/getcfg.cgs
    sim/testsuite/sim/sh64/media/getcon.cgs
    sim/testsuite/sim/sh64/media/gettr.cgs
    sim/testsuite/sim/sh64/media/icbi.cgs
    sim/testsuite/sim/sh64/media/ldb.cgs
    sim/testsuite/sim/sh64/media/ldhil.cgs
    sim/testsuite/sim/sh64/media/ldhiq.cgs
    sim/testsuite/sim/sh64/media/ldl.cgs
    sim/testsuite/sim/sh64/media/ldlol.cgs
    sim/testsuite/sim/sh64/media/ldloq.cgs
    sim/testsuite/sim/sh64/media/ldq.cgs
    sim/testsuite/sim/sh64/media/ldub.cgs
    sim/testsuite/sim/sh64/media/lduw.cgs
    sim/testsuite/sim/sh64/media/ldw.cgs
    sim/testsuite/sim/sh64/media/ldxb.cgs
    sim/testsuite/sim/sh64/media/ldxl.cgs
    sim/testsuite/sim/sh64/media/ldxq.cgs
    sim/testsuite/sim/sh64/media/ldxub.cgs
    sim/testsuite/sim/sh64/media/ldxuw.cgs
    sim/testsuite/sim/sh64/media/ldxw.cgs
    sim/testsuite/sim/sh64/media/mabsl.cgs
    sim/testsuite/sim/sh64/media/mabsw.cgs
    sim/testsuite/sim/sh64/media/maddl.cgs
    sim/testsuite/sim/sh64/media/maddsl.cgs
    sim/testsuite/sim/sh64/media/maddsub.cgs
    sim/testsuite/sim/sh64/media/maddsw.cgs
    sim/testsuite/sim/sh64/media/maddw.cgs
    sim/testsuite/sim/sh64/media/mcmpeqb.cgs
    sim/testsuite/sim/sh64/media/mcmpeql.cgs
    sim/testsuite/sim/sh64/media/mcmpeqw.cgs
    sim/testsuite/sim/sh64/media/mcmpgtl.cgs
    sim/testsuite/sim/sh64/media/mcmpgtub.cgs
    sim/testsuite/sim/sh64/media/mcmpgtw.cgs
    sim/testsuite/sim/sh64/media/mcmv.cgs
    sim/testsuite/sim/sh64/media/mcnvslw.cgs
    sim/testsuite/sim/sh64/media/mcnvswb.cgs
    sim/testsuite/sim/sh64/media/mcnvswub.cgs
    sim/testsuite/sim/sh64/media/mextr1.cgs
    sim/testsuite/sim/sh64/media/mextr2.cgs
    sim/testsuite/sim/sh64/media/mextr3.cgs
    sim/testsuite/sim/sh64/media/mextr4.cgs
    sim/testsuite/sim/sh64/media/mextr5.cgs
    sim/testsuite/sim/sh64/media/mextr6.cgs
    sim/testsuite/sim/sh64/media/mextr7.cgs
    sim/testsuite/sim/sh64/media/mmacfxwl.cgs
    sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
    sim/testsuite/sim/sh64/media/mmulfxl.cgs
    sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
    sim/testsuite/sim/sh64/media/mmulfxw.cgs
    sim/testsuite/sim/sh64/media/mmulhiwl.cgs
    sim/testsuite/sim/sh64/media/mmull.cgs
    sim/testsuite/sim/sh64/media/mmullowl.cgs
    sim/testsuite/sim/sh64/media/mmulsumwq.cgs
    sim/testsuite/sim/sh64/media/mmulw.cgs
    sim/testsuite/sim/sh64/media/movi.cgs
    sim/testsuite/sim/sh64/media/mpermw.cgs
    sim/testsuite/sim/sh64/media/msadubq.cgs
    sim/testsuite/sim/sh64/media/mshaldsl.cgs
    sim/testsuite/sim/sh64/media/mshaldsw.cgs
    sim/testsuite/sim/sh64/media/mshardl.cgs
    sim/testsuite/sim/sh64/media/mshardsq.cgs
    sim/testsuite/sim/sh64/media/mshardw.cgs
    sim/testsuite/sim/sh64/media/mshfhib.cgs
    sim/testsuite/sim/sh64/media/mshfhil.cgs
    sim/testsuite/sim/sh64/media/mshfhiw.cgs
    sim/testsuite/sim/sh64/media/mshflob.cgs
    sim/testsuite/sim/sh64/media/mshflol.cgs
    sim/testsuite/sim/sh64/media/mshflow.cgs
    sim/testsuite/sim/sh64/media/mshlldl.cgs
    sim/testsuite/sim/sh64/media/mshlldw.cgs
    sim/testsuite/sim/sh64/media/mshlrdl.cgs
    sim/testsuite/sim/sh64/media/mshlrdw.cgs
    sim/testsuite/sim/sh64/media/msubl.cgs
    sim/testsuite/sim/sh64/media/msubsl.cgs
    sim/testsuite/sim/sh64/media/msubsub.cgs
    sim/testsuite/sim/sh64/media/msubsw.cgs
    sim/testsuite/sim/sh64/media/msubw.cgs
    sim/testsuite/sim/sh64/media/mulsl.cgs
    sim/testsuite/sim/sh64/media/mulul.cgs
    sim/testsuite/sim/sh64/media/nop.cgs
    sim/testsuite/sim/sh64/media/nsb.cgs
    sim/testsuite/sim/sh64/media/ocbi.cgs
    sim/testsuite/sim/sh64/media/ocbp.cgs
    sim/testsuite/sim/sh64/media/ocbwb.cgs
    sim/testsuite/sim/sh64/media/or.cgs
    sim/testsuite/sim/sh64/media/ori.cgs
    sim/testsuite/sim/sh64/media/prefi.cgs
    sim/testsuite/sim/sh64/media/pta.cgs
    sim/testsuite/sim/sh64/media/ptabs.cgs
    sim/testsuite/sim/sh64/media/ptb.cgs
    sim/testsuite/sim/sh64/media/ptrel.cgs
    sim/testsuite/sim/sh64/media/putcfg.cgs
    sim/testsuite/sim/sh64/media/putcon.cgs
    sim/testsuite/sim/sh64/media/rte.cgs
    sim/testsuite/sim/sh64/media/shard.cgs
    sim/testsuite/sim/sh64/media/shardl.cgs
    sim/testsuite/sim/sh64/media/shari.cgs
    sim/testsuite/sim/sh64/media/sharil.cgs
    sim/testsuite/sim/sh64/media/shlld.cgs
    sim/testsuite/sim/sh64/media/shlldl.cgs
    sim/testsuite/sim/sh64/media/shlli.cgs
    sim/testsuite/sim/sh64/media/shllil.cgs
    sim/testsuite/sim/sh64/media/shlrd.cgs
    sim/testsuite/sim/sh64/media/shlrdl.cgs
    sim/testsuite/sim/sh64/media/shlri.cgs
    sim/testsuite/sim/sh64/media/shlril.cgs
    sim/testsuite/sim/sh64/media/shori.cgs
    sim/testsuite/sim/sh64/media/sleep.cgs
    sim/testsuite/sim/sh64/media/stb.cgs
    sim/testsuite/sim/sh64/media/sthil.cgs
    sim/testsuite/sim/sh64/media/sthiq.cgs
    sim/testsuite/sim/sh64/media/stl.cgs
    sim/testsuite/sim/sh64/media/stlol.cgs
    sim/testsuite/sim/sh64/media/stloq.cgs
    sim/testsuite/sim/sh64/media/stq.cgs
    sim/testsuite/sim/sh64/media/stw.cgs
    sim/testsuite/sim/sh64/media/stxb.cgs
    sim/testsuite/sim/sh64/media/stxl.cgs
    sim/testsuite/sim/sh64/media/stxq.cgs
    sim/testsuite/sim/sh64/media/stxw.cgs
    sim/testsuite/sim/sh64/media/sub.cgs
    sim/testsuite/sim/sh64/media/subl.cgs
    sim/testsuite/sim/sh64/media/swapq.cgs
    sim/testsuite/sim/sh64/media/synci.cgs
    sim/testsuite/sim/sh64/media/synco.cgs
    sim/testsuite/sim/sh64/media/testutils.inc
    sim/testsuite/sim/sh64/media/trapa.cgs
    sim/testsuite/sim/sh64/media/xor.cgs
    sim/testsuite/sim/sh64/media/xori.cgs
    sim/testsuite/sim/sh64/misc/fr-dr.s

11 files changed, 216 insertions, 18 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 8f00e91..e2c90f8 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,8 +1,24 @@
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* floatformat.h (enum floatformat_byteorders): Add
+	floatformat_vax.
+	(floatformat_vax_aingle, floatformat_vax_double): Declare.
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
+	more exotic underlying types to be used.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	disasm.h: Add declaration for print_insn_z80
+
 2005-09-30  Catherine Moore  <clm@cm00re.com>
 
 	* dis-asm.h (print_insn_bfin): Declare.
-	* elf/bfin.h: New file.
-	* elf/common.h (EM_BLACKFIN): Define.
 	* opcode/bfin.h: New file.
 
 2005-09-26  Mark Mitchell  <mark@codesourcery.com>
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index ca201a1..a8b66cc 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,8 @@
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* internal.h: Add relocation number for Z80
+	* z80.h: New file.
+
 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 
 	* a29k.h: Delete.
diff --git a/include/coff/internal.h b/include/coff/internal.h
index 20e06c2..d7a8381 100644
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -1,7 +1,7 @@
 /* Internal format of COFF object file data structures, for GNU BFD.
    This file is part of BFD, the Binary File Descriptor library.
    
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004. 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -715,6 +715,10 @@ struct internal_reloc
 #define R_IMM4H   0x24		/* high nibble */
 #define R_DISP7   0x25          /* djnz displacement */
 
+/* Z80 modes */
+#define R_OFF8    0x32		/* 8 bit signed abs, for (i[xy]+d) */
+/* R_JR, R_IMM8, R_IMM16, R_IMM32 - as for Z8k */
+
 /* H8500 modes */
 
 #define R_H8500_IMM8  	1		/*  8 bit immediate 	*/
diff --git a/include/coff/z80.h b/include/coff/z80.h
new file mode 100644
index 0000000..3c72c10
--- /dev/null
+++ b/include/coff/z80.h
@@ -0,0 +1,51 @@
+/* coff information for Zilog Z80
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+/* z80 backend does not use dots in section names.  */
+#undef  _TEXT
+#define _TEXT "text"
+#undef  _DATA
+#define _DATA "data"
+#undef  _BSS
+#define _BSS "bss"
+
+/* Type of cpu is stored in flags.  */
+#define F_MACHMASK 0xF000
+
+#define	Z80MAGIC   0x805A
+
+#define Z80BADMAG(x) (((x).f_magic != Z80MAGIC))
+
+/* Relocation directives.  */
+
+/* This format actually has more bits than we need.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
diff --git a/include/dis-asm.h b/include/dis-asm.h
index dd4e86e..ca6da9c 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -78,7 +78,7 @@ typedef struct disassemble_info {
      for processors with run-time-switchable instruction sets.  The default,
      zero, means that there is no constraint.  CGEN-based opcodes ports
      may use ISA_foo masks.  */
-  unsigned long insn_sets;
+  void *insn_sets;
 
   /* Some targets need information about the current section to accurately
      display insns.  If this is NULL, the target disassembler function
@@ -208,6 +208,7 @@ extern int print_insn_i370		(bfd_vma, disassemble_info *);
 extern int print_insn_m68hc11		(bfd_vma, disassemble_info *);
 extern int print_insn_m68hc12		(bfd_vma, disassemble_info *);
 extern int print_insn_m68k		(bfd_vma, disassemble_info *);
+extern int print_insn_z80		(bfd_vma, disassemble_info *);
 extern int print_insn_z8001		(bfd_vma, disassemble_info *);
 extern int print_insn_z8002		(bfd_vma, disassemble_info *);
 extern int print_insn_h8300		(bfd_vma, disassemble_info *);
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index cf4b578..485a78e 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+	* common.h (EM_BLACKFIN): Define.
+
 2005-10-08  Paul Brook  <paul@codesourcery.com>
 
 	* arm.h: Add prototypes for BFD object attribute routines.
diff --git a/include/floatformat.h b/include/floatformat.h
index a244874..f1bd7f6 100644
--- a/include/floatformat.h
+++ b/include/floatformat.h
@@ -29,25 +29,26 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
    (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
    contains with the *_start and *_len fields.  */
 
-/* What is the order of the bytes. */
+/* What is the order of the bytes?  */
 
 enum floatformat_byteorders {
-
   /* Standard little endian byte order.
      EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
-
   floatformat_little,
 
   /* Standard big endian byte order.
      EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
-
   floatformat_big,
 
   /* Little endian byte order but big endian word order.
      EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
+  floatformat_littlebyte_bigword,
 
-  floatformat_littlebyte_bigword
-
+  /* VAX byte order.  Little endian byte order with 16-bit words.  The
+     following example is an illustration of the byte order only; VAX
+     doesn't have a fully IEEE compliant floating-point format.
+     EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */
+  floatformat_vax
 };
 
 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
@@ -97,6 +98,12 @@ extern const struct floatformat floatformat_ieee_double_little;
 
 extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
 
+/* floatformats for VAX.  */
+
+extern const struct floatformat floatformat_vax_f;
+extern const struct floatformat floatformat_vax_d;
+extern const struct floatformat floatformat_vax_g;
+
 /* floatformats for various extendeds.  */
 
 extern const struct floatformat floatformat_i387_ext;
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 0802870..a282a62 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,43 @@
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2005-02-16  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
+	cgen_isa_mask_* to cgen_bitset_*.
+	* cgen.h: Likewise.
+
+	2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
+	(CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
+	(CGEN_CPU_TABLE): Make isas a ponter.
+
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
+	(CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
+	(CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
+
+	2002-12-13  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (symcat.h): #include it.
+	(cgen-bitset.h): #include it.
+	(CGEN_ATTR_VALUE_TYPE): Now a union.
+	(CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
+	(CGEN_ATTR_ENTRY): 'value' now unsigned.
+	(cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
+	* cgen-bitset.h: New file.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* ia64.h (enum ia64_opnd): Move memory operand out of set of
+	indirect operands.
+
 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
 	* hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
diff --git a/include/opcode/cgen-bitset.h b/include/opcode/cgen-bitset.h
new file mode 100644
index 0000000..1b6fbe3
--- /dev/null
+++ b/include/opcode/cgen-bitset.h
@@ -0,0 +1,55 @@
+/* Header file the type CGEN_BITSET.
+
+Copyright 2002, 2005 Free Software Foundation, Inc.
+
+This file is part of GDB, the GNU debugger, and the GNU Binutils.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+#ifndef CGEN_BITSET_H
+#define CGEN_BITSET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* A bitmask represented as a string.
+   Each member of the set is represented as a bit
+   in the string. Bytes are indexed from left to right in the string and
+   bits from most significant to least within each byte.
+
+   For example, the bit representing member number 6 is (set->bits[0] & 0x02).
+*/
+typedef struct cgen_bitset
+{
+  unsigned length;
+  char *bits;
+} CGEN_BITSET;
+
+extern CGEN_BITSET *cgen_bitset_create PARAMS ((unsigned));
+extern void cgen_bitset_init PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_clear PARAMS ((CGEN_BITSET *));
+extern void cgen_bitset_add PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_set PARAMS ((CGEN_BITSET *, unsigned));
+extern int cgen_bitset_compare PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern void cgen_bitset_union PARAMS ((CGEN_BITSET *, CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_intersect_p PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_contains PARAMS ((CGEN_BITSET *, unsigned));
+extern CGEN_BITSET *cgen_bitset_copy PARAMS ((CGEN_BITSET *));
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h
index efebadb..e8fd5d3 100644
--- a/include/opcode/cgen.h
+++ b/include/opcode/cgen.h
@@ -22,6 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef CGEN_H
 #define CGEN_H
 
+#include "symcat.h"
+#include "cgen-bitset.h"
 /* ??? This file requires bfd.h but only to get bfd_vma.
    Seems like an awful lot to require just to get such a fundamental type.
    Perhaps the definition of bfd_vma can be moved outside of bfd.h.
@@ -107,7 +109,13 @@ typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
 
 /* Type of attribute values.  */
 
-typedef int CGEN_ATTR_VALUE_TYPE;
+typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
+typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
+typedef union
+{
+  CGEN_ATTR_VALUE_BITSET_TYPE bitset;
+  CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
+} CGEN_ATTR_VALUE_TYPE;
 
 /* Struct to record attribute information.  */
 
@@ -153,7 +161,9 @@ struct { unsigned int bool; \
 #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
 ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
  ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
- : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET]))
+ : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
+#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
+ ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
 
 /* Attribute name/value tables.
    These are used to assist parsing of descriptions at run-time.  */
@@ -161,7 +171,7 @@ struct { unsigned int bool; \
 typedef struct
 {
   const char * name;
-  CGEN_ATTR_VALUE_TYPE value;
+  unsigned value;
 } CGEN_ATTR_ENTRY;
 
 /* For each domain (ifld,hw,operand,insn), list of attributes.  */
@@ -965,6 +975,7 @@ typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS = 0
 } CGEN_INSN_ATTR;
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
 #endif
 
 /* This struct defines each entry in the instruction table.  */
@@ -1016,6 +1027,8 @@ typedef struct
 /* Return value of attribute ATTR in INSN.  */
 #define CGEN_INSN_ATTR_VALUE(insn, attr) \
 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
+#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
+  CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
 } CGEN_IBASE;
 
 /* Return non-zero if INSN is the "invalid" insn marker.  */
@@ -1179,10 +1192,9 @@ typedef struct cgen_cpu_desc
   /* Bitmap of selected machine(s) (a la BFD machine number).  */
   int machs;
 
-  /* Bitmap of selected isa(s).
-     ??? Simultaneous multiple isas might not make sense, but it's not (yet)
-     precluded.  */
-  int isas;
+  /* Bitmap of selected isa(s).  */
+  CGEN_BITSET *isas;
+#define CGEN_CPU_ISAS(cd) ((cd)->isas)
 
   /* Current endian.  */
   enum cgen_endian endian;
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index 58553b3..164594b 100644
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -75,13 +75,15 @@ enum ia64_opnd
     IA64_OPND_R3,	/* third register # */
     IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
 
+    /* memory operands: */
+    IA64_OPND_MR3,	/* memory at addr of third register # */
+
     /* indirect operands: */
     IA64_OPND_CPUID_R3,	/* cpuid[reg] */
     IA64_OPND_DBR_R3,	/* dbr[reg] */
     IA64_OPND_DTR_R3,	/* dtr[reg] */
     IA64_OPND_ITR_R3,	/* itr[reg] */
     IA64_OPND_IBR_R3,	/* ibr[reg] */
-    IA64_OPND_MR3,	/* memory at addr of third register # */
     IA64_OPND_MSR_R3,	/* msr[reg] */
     IA64_OPND_PKR_R3,	/* pkr[reg] */
     IA64_OPND_PMC_R3,	/* pmc[reg] */