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authorRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:54:30 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:54:30 +0100
commitd50c751e00b5336b4604b92271ab84615fdb0d27 (patch)
treea03ccbb9798577e978217f1c9639300afb0fec2a /include
parentf11ad6bc0fc44b94c6970115bb6984b497b967e7 (diff)
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[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication
This patch adds qualifiers to represent /z and /m suffixes on predicate registers. include/ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. (AARCH64_OPND_QLF_P_M): Likewise. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for AARCH64_OPND_QLF_P_[ZM]. (aarch64_print_operand): Print /z and /m where appropriate. gas/ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge. (parse_vector_type_for_operand): Assert that the skipped character is a '.'. (parse_predication_for_operand): New function. (parse_typed_reg): Parse /z and /m suffixes for predicate registers. (vectype_to_qualifier): Handle NT_zero and NT_merge.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog5
-rw-r--r--include/opcode/aarch64.h3
2 files changed, 8 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 53d0ba0..175d1d5 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
+ (AARCH64_OPND_QLF_P_M): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index b0eb617..8eae0b9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -315,6 +315,9 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_V_2D,
AARCH64_OPND_QLF_V_1Q,
+ AARCH64_OPND_QLF_P_Z,
+ AARCH64_OPND_QLF_P_M,
+
/* Constraint on value. */
AARCH64_OPND_QLF_imm_0_7,
AARCH64_OPND_QLF_imm_0_15,