update doc for sparclite 934 opcode table changes

1 files changed, 20 insertions, 22 deletions

diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 316b647..c8be2fe 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -1,5 +1,3 @@
-/* to sanitize this file, grep -v v9 < sparc.h > clean-sparc.h */
-
 /* Definitions for opcode table for the sparc.
 	Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
 
@@ -22,17 +20,13 @@ along with GAS or GDB; see the file COPYING.	If not, write to
 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.	*/
 
 /* The SPARC opcode table (and other related data) is defined in
-   the BFD library in opc-sparc.c.  If you change anything here, make
+   the opcodes library in sparc-opc.c.  If you change anything here, make
    sure you fix up that file, and vice versa.  */
 
  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
     instruction's name rather than the args.  This would make gas faster, pinsn
     slower, but would mess up some macros a bit.  xoxorich. */
 
-#if !defined(__STDC__) && !defined(const)
-#define const
-#endif
-
 #define sparc_architecture	bfd_sparc_architecture
 #define architecture_pname	bfd_sparc_architecture_pname
 #define sparc_opcode		bfd_sparc_opcode
@@ -69,6 +63,11 @@ struct sparc_opcode {
 
 #define	F_DELAYED	1	/* Delayed branch */
 #define	F_ALIAS		2	/* Alias for a "real" instruction */
+#define	F_UNBR		4	/* Unconditional branch */
+#define	F_CONDBR	8	/* Conditional branch */
+#define	F_JSR		16	/* Subroutine call */
+/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
+/* FIXME: Add F_OBSOLETE flag for v9, for instructions that no longer exist? */
 
 /*
 
@@ -92,9 +91,6 @@ Kinds of operands:
 	f	frs2 floating point register.
 	B	frs2 floating point register (double/even).
 	R	frs2 floating point register (quad/multiple of 4).
-	j	frs3 floating point register. (v9)
-	u	frs3 floating point register. (double/even) (v9)
-	U	frs3 floating point register. (quad/multiple of 4) (v9)
 	g	frsd floating point register.
 	H	frsd floating point register (double/even).
 	J	frsd floating point register (quad/multiple of 4).
@@ -104,7 +100,8 @@ Kinds of operands:
 	m	alternate space register (asr) in rd
 	M	alternate space register (asr) in rs1
 	h	22 high bits.
-	K	MEMBAR mask (4 bits). (v9)
+	K	MEMBAR mask (7 bits). (v9)
+	j	10 bit Immediate. (v9)
 	I	11 bit Immediate. (v9)
 	i	13 bit Immediate.
 	n	22 bit immediate.
@@ -119,8 +116,8 @@ Kinds of operands:
 	p	Processor state register.
 	N	Branch predict clear ",pn" (v9)
 	T	Branch predict set ",pt" (v9)
-	z	icc. (v9)
-	Z	xcc. (v9)
+	z	%icc. (v9)
+	Z	%xcc. (v9)
 	q	Floating point queue.
 	r	Single register that is both rs1 and rsd.
 	Q	Coprocessor queue.
@@ -128,21 +125,22 @@ Kinds of operands:
 	t	Trap base register.
 	w	Window invalid mask register.
 	y	Y register.
-	Y	%amr (v9?)
+	E	%ccr. (v9)
+	s	%fprs. (v9)
 	P	%pc.  (v9)
-	E	%modes.  (v9)
 	W	%tick.	(v9)
-	s	%usr. (v9)
 	o	%asi. (v9)
-	6	fcc0. (v9)
-	7	fcc1. (v9)
-	8	fcc2. (v9)
-	9	fcc3. (v9)
+	6	%fcc0. (v9)
+	7	%fcc1. (v9)
+	8	%fcc2. (v9)
+	9	%fcc3. (v9)
 	!	Privileged Register in rd (v9)
 	?	Privileged Register in rs1 (v9)
+	*	Prefetch function constant. (v9)
+	x	OPF field (v9 impdep).
 
 The following chars are unused: (note: ,[] are used as punctuation)
-[osxOX3450]
+[uxOUXY3450]
 
 */
 
@@ -150,7 +148,7 @@ The following chars are unused: (note: ,[] are used as punctuation)
 #define OP3(x)		(((x)&0x3f) << 19) /* op3 field of format3 insns */
 #define OP(x)		((unsigned)((x)&0x3) << 30) /* op field of all insns */
 #define OPF(x)		(((x)&0x1ff) << 5) /* opf field of float insns */
-#define OPF_LOW(x)	OPF((x)&0xf) /* v9 */
+#define OPF_LOW5(x)	OPF((x)&0x1f) /* v9 */
 #define F3F(x, y, z)	(OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
 #define F3I(x)		(((x)&0x1) << 13) /* immediate field of format 3 insns */
 #define F2(x, y)	(OP(x) | OP2(y)) /* format 2 insns */