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| author | Alan Modra <amodra@gmail.com> | 2019-03-28 10:36:55 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2019-03-28 15:21:05 +1030 |
| commit | 96a86c01d119372f4af5aff2501d3104e6c1a8e3 (patch) | |
| tree | cbd1ac115b85d52e073ee0ca7b2ffd31901a3395 /include | |
| parent | 072029171354eee0e2f90527196ddda5a85e98c1 (diff) | |
| download | gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.zip gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.tar.gz gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.tar.bz2 | |
PR24390, Don't decode mtfsb field as a cr field
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 5 |
2 files changed, 9 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index ae79b9f..f6662f7 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2019-03-28 Alan Modra <amodra@gmail.com> + + PR 24390 + * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. + 2019-03-25 Tamar Christina <tamar.christina@arm.com> * dis-asm.h (struct disassemble_info): Add stop_offset. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 6bdf246..7a0bc60 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -354,7 +354,10 @@ extern const unsigned int num_powerpc_operands; #define PPC_OPERAND_CR_BIT (0x20) /* This is a CR FIELD that does not use symbolic names (unless - -mregnames is in effect). */ + -mregnames is in effect). If both PPC_OPERAND_CR_BIT and + PPC_OPERAND_CR_REG are set then treat the field as per + PPC_OPERAND_CR_BIT for assembly, but as if neither of these + bits are set for disassembly. */ #define PPC_OPERAND_CR_REG (0x40) /* This operand names a special purpose register. */ |