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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-01 10:43:25 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-01 10:51:03 +0000 |
commit | 3197e593d8a2a79a23dc9155d18d7aff6281da14 (patch) | |
tree | e6c241fb399f4c80a9ce4eb60a598da39306c5b0 /include | |
parent | 94c9216c03ab1af16b1bdd11a10a66c13e6458d8 (diff) | |
download | gdb-3197e593d8a2a79a23dc9155d18d7aff6281da14.zip gdb-3197e593d8a2a79a23dc9155d18d7aff6281da14.tar.gz gdb-3197e593d8a2a79a23dc9155d18d7aff6281da14.tar.bz2 |
arm: add armv9-a architecture to -march
Update also include:
+ New value of Tag_CPU_arch EABI attribute (22) is added.
+ Updated missing Tag_CPU_arch EABI attributes.
+ Updated how we combine archs 'v4t_plus_v6_m' as this mechanism
have to handle new Armv9 as well.
Regression tested on `arm-none-eabi` cross Binutils and no issues.
bfd/
* archures.c: Define bfd_mach_arm_9.
* bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9.
* cpu-arm.c: Add 'armv9-a' option to -march.
* elf32-arm.c (using_thumb2_bl): Update assert check.
(arch_has_arm_nop): Add TAG_CPU_ARCH_V9.
(bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9.
Update assert.
(tag_cpu_arch_combine): Updated table.
(v9): New table..
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Update with
elfcpp/
* arm.h: Update TAG_CPU_ARCH_ enums with correct values.
gas/
* NEWS: Update docs.
* config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a
for -amarch=all.
(aeabi_set_public_attributes): Update assert.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/armv9-a_arch.d: New test.
* testsuite/gas/arm/attr-march-all.d: Update test with v9.
include/
* elf/arm.h Update TAG_CPU_ARCH_ defines with correct values.
* opcode/arm.h (ARM_EXT3_V9A): New macro.
(ARM_ARCH_NONE): Updated with arm_feature_set.core size.
(FPU_NONE): Updated.
(ARM_ANY): Updated.
(ARM_ARCH_UNKNOWN): New macro.
(ARM_FEATURE_LOW): Updated.
(ARM_FEATURE_CORE): Updated.
(ARM_FEATURE_CORE_LOW): Updated.
(ARM_FEATURE_CORE_HIGH): Updated.
(ARM_FEATURE_COPROC): Updated.
(ARM_FEATURE): Updated.
(ARM_FEATURE_ALL): New macro.
opcodes/
* arm-dis.c (select_arm_features): Support bfd_mach_arm_9.
Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
Diffstat (limited to 'include')
-rw-r--r-- | include/elf/arm.h | 6 | ||||
-rw-r--r-- | include/opcode/arm.h | 31 |
2 files changed, 25 insertions, 12 deletions
diff --git a/include/elf/arm.h b/include/elf/arm.h index 299f394..8213b90 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -111,8 +111,12 @@ #define TAG_CPU_ARCH_V8R 15 #define TAG_CPU_ARCH_V8M_BASE 16 #define TAG_CPU_ARCH_V8M_MAIN 17 +#define TAG_CPU_ARCH_8_1A 18 +#define TAG_CPU_ARCH_8_2A 19 +#define TAG_CPU_ARCH_8_3A 20 #define TAG_CPU_ARCH_V8_1M_MAIN 21 -#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8_1M_MAIN +#define TAG_CPU_ARCH_V9 22 +#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V9 /* Pseudo-architecture to allow objects to be compatible with the subset of armv4t and armv6-m. This value should never be stored in object files. */ #define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1) diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 4a6044f..cf72b90 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -94,6 +94,7 @@ Authentication and Branch Target Identification Extension. */ +#define ARM_EXT3_V9A 0x00000002 /* Armv9-A. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ @@ -385,11 +386,16 @@ #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) #define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \ ARM_AEXT2_V8_1M_MAIN) +#define ARM_ARCH_V9A ARM_FEATURE_ALL(ARM_AEXT_V8A, \ + ARM_AEXT2_V8_5A | ARM_EXT2_CRC, \ + ARM_EXT3_V9A, \ + FPU_NEON_EXT_RDMA | FPU_NEON_EXT_DOTPROD) /* Some useful combinations: */ -#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) -#define FPU_NONE ARM_FEATURE_LOW (0, 0) -#define ARM_ANY ARM_FEATURE (-1, -1 & ~ (ARM_EXT2_MVE | ARM_EXT2_MVE_FP), 0) /* Any basic core. */ +#define ARM_ARCH_NONE ARM_FEATURE_ALL (0, 0, 0, 0) +#define FPU_NONE ARM_FEATURE_ALL (0, 0, 0, 0) +#define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */ +#define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */ #define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */ #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) /* Extensions containing some Thumb-2 instructions. If any is present, Thumb @@ -429,8 +435,8 @@ /* There are too many feature bits to fit in a single word, so use a structure. For simplicity we put all core features in array CORE - and everything else in the other. All the bits in element core[0] - have been occupied, so new feature should use bit in element core[1] + and everything else in the other. All the bits in element core[0:1] + have been occupied, so new feature should use bit in element core[2] and use macro ARM_FEATURE to initialize the feature set variable. */ typedef struct { @@ -494,10 +500,13 @@ typedef struct && (T1).core[1] == (T2).core[1] \ && (T1).core[2] == (T2).core[2]) -#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} -#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} -#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} -#define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} +#define ARM_FEATURE_LOW(core, coproc) {{(core), 0, 0}, (coproc)} +#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2), 0}, 0} +#define ARM_FEATURE_CORE_LOW(core) {{(core), 0, 0}, 0} +#define ARM_FEATURE_CORE_HIGH(core) {{0, (core), 0}, 0} #define ARM_FEATURE_CORE_HIGH_HIGH(core) {{0, 0, (core)}, 0} -#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} -#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} +#define ARM_FEATURE_COPROC(coproc) {{0, 0, 0}, (coproc)} +#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2), 0}, (coproc)} +/* Below macro is used to set all fields in arm_feature_set struct. +*/ +#define ARM_FEATURE_ALL(core1, core2, core3, coproc) {{(core1), (core2), (core3)}, (coproc)} |