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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:45:35 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:06:52 +0100 |
| commit | 13c60ad7e1211ee1dfbf6bfb5e35110a33e4eed5 (patch) | |
| tree | 7069b9d866404ee4f259bcea0f4d86b107d8bf02 /include | |
| parent | 70d561813cd4da84109395c36662a187411a4d97 (diff) | |
| download | gdb-13c60ad7e1211ee1dfbf6bfb5e35110a33e4eed5.zip gdb-13c60ad7e1211ee1dfbf6bfb5e35110a33e4eed5.tar.gz gdb-13c60ad7e1211ee1dfbf6bfb5e35110a33e4eed5.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 9 |
2 files changed, 14 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 2ccf741..8941d87 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New. + (AARCH64_FEATURE_FRINTTS): New. + (AARCH64_ARCH_V8_5): Add both by default. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New. (AARCH64_ARCH_V8_5): New. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index f8ae42f..fb20bd7 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -64,6 +64,11 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ #define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */ +/* Flag Manipulation insns. */ +#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL +/* FRINT[32,64][Z,X] insns. */ +#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL + /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ AARCH64_FEATURE_FP \ @@ -87,7 +92,9 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_DOTPROD \ | AARCH64_FEATURE_F16_FML) #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ - AARCH64_FEATURE_V8_5) + AARCH64_FEATURE_V8_5 \ + | AARCH64_FEATURE_FLAGMANIP \ + | AARCH64_FEATURE_FRINTTS) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |