diff options
| author | Adam Nemet <anemet@caviumnetworks.com> | 2008-02-04 19:25:05 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@caviumnetworks.com> | 2008-02-04 19:25:05 +0000 |
| commit | e642969943f894f3930ffc174cdf3e9bd75941ad (patch) | |
| tree | 8bd5a782eb168699babb51b07abfae7f24e40e29 /include | |
| parent | 7b03d09a44d75b59cd31e89d752c5c52b39a03b9 (diff) | |
| download | gdb-e642969943f894f3930ffc174cdf3e9bd75941ad.zip gdb-e642969943f894f3930ffc174cdf3e9bd75941ad.tar.gz gdb-e642969943f894f3930ffc174cdf3e9bd75941ad.tar.bz2 | |
* mips.h: Update copyright.
(INSN_CHIP_MASK): New macro.
(INSN_OCTEON): New macro.
(CPU_OCTEON): New macro.
(OPCODE_IS_MEMBER): Handle Octeon instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 8 | ||||
| -rw-r--r-- | include/opcode/mips.h | 13 |
2 files changed, 18 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index afd480b..9edf24c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2008-02-04 Adam Nemet <anemet@caviumnetworks.com> + + * mips.h: Update copyright. + (INSN_CHIP_MASK): New macro. + (INSN_OCTEON): New macro. + (CPU_OCTEON): New macro. + (OPCODE_IS_MEMBER): Handle Octeon instructions. + 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> * mips.h (INSN_LOONGSON_2E): New. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 20638d8..6ddc9d0 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1,6 +1,6 @@ /* mips.h. Mips opcode list for GDB, the GNU debugger. Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005 + 2003, 2004, 2005, 2008 Free Software Foundation, Inc. Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support @@ -510,6 +510,12 @@ struct mips_opcode static const unsigned int mips_isa_table[] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; +/* Masks used for Chip specific instructions. */ +#define INSN_CHIP_MASK 0xc3ff0800 + +/* Cavium Networks Octeon instructions. */ +#define INSN_OCTEON 0x00000800 + /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x3c00f000 @@ -521,8 +527,6 @@ static const unsigned int mips_isa_table[] = /* MIPS-3D ASE */ #define INSN_MIPS3D 0x00008000 -/* Chip specific instructions. These are bitmasks. */ - /* MIPS R4650 instruction. */ #define INSN_4650 0x00010000 /* LSI R4010 instruction. */ @@ -605,6 +609,7 @@ static const unsigned int mips_isa_table[] = #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 +#define CPU_OCTEON 6501 /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified @@ -635,6 +640,8 @@ static const unsigned int mips_isa_table[] = && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ || (cpu == CPU_LOONGSON_2F \ && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ + || (cpu == CPU_OCTEON \ + && ((insn)->membership & INSN_OCTEON) != 0) \ || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. |