[binutils][aarch64] Bfloat16 enablement [2/X]

Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (vectype_to_qualifier): Special case the
	S_2H operand qualifier.
	* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
	* testsuite/gas/aarch64/bfloat16.d: New test.
	* testsuite/gas/aarch64/bfloat16.s: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
	(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
	(enum aarch64_opnd_qualifier): Introduce new operand qualifier
	AARCH64_OPND_QLF_S_2H.
	(enum aarch64_insn_class): Introduce new class "bfloat16".
	(BFLOAT16_SVE_INSNC): New feature set for bfloat16
	instructions to support the movprfx constraint.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-dis-2.c (aarch64_opcode_lookup_1,
	aarch64_find_next_opcode): Account for new instructions.
	* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-opc.c (struct operand_qualifier_data): Add data for
	new AARCH64_OPND_QLF_S_2H qualifier.
	* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
	QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
	(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
	aarch64_feature_bfloat16_bfmmla4): New feature sets.
	(BFLOAT_SVE, BFLOAT): New feature set macros.
	(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
	to define BFloat16 instructions.
	(aarch64_opcode_table): Define new instructions bfdot,
	bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
	bfcvtn2, bfcvt.

Regression tested on aarch64-elf.

Is it ok for trunk?

Regards,
Mihail

2 files changed, 21 insertions, 5 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 246dc49..d7c891d 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,6 +1,17 @@
 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 
+	* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
+	(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
+	(enum aarch64_opnd_qualifier): Introduce new operand qualifier
+	AARCH64_OPND_QLF_S_2H.
+	(enum aarch64_insn_class): Introduce new class "bfloat16".
+	(BFLOAT16_SVE_INSNC): New feature set for bfloat16
+	instructions to support the movprfx constraint.
+
+2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
+2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
+
 	* opcode/aarch64.h (AARCH64_FEATURE_V8_6): New.
 	(AARCH64_ARCH_V8_6): New.
 
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 493e8f8..4cda1e0 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -64,6 +64,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_F16_FML	0x1000000000ULL	/* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5	0x2000000000ULL	/* ARMv8.5 processors.  */
 #define AARCH64_FEATURE_V8_6	0x00000002	/* ARMv8.6 processors.  */
+#define AARCH64_FEATURE_BFLOAT16	0x00000004	/* Bfloat16 insns.  */
 
 /* Flag Manipulation insns.  */
 #define AARCH64_FEATURE_FLAGMANIP	0x4000000000ULL
@@ -131,7 +132,8 @@ typedef uint32_t aarch64_insn;
 						 | AARCH64_FEATURE_ID_PFR2 \
 						 | AARCH64_FEATURE_SSBS)
 #define AARCH64_ARCH_V8_6	AARCH64_FEATURE (AARCH64_ARCH_V8_5,	\
-						 AARCH64_FEATURE_V8_6)
+						 AARCH64_FEATURE_V8_6   \
+						 | AARCH64_FEATURE_BFLOAT16)
 
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
@@ -462,11 +464,13 @@ enum aarch64_opnd_qualifier
   AARCH64_OPND_QLF_S_S,
   AARCH64_OPND_QLF_S_D,
   AARCH64_OPND_QLF_S_Q,
-  /* This type qualifier has a special meaning in that it means that 4 x 1 byte
-     are selected by the instruction.  Other than that it has no difference
-     with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
-     reasons and is an exception from normal AArch64 disassembly scheme.  */
+  /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
+     or 2 x 2 byte are selected by the instruction.  Other than that they have
+     no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
+     for syntactical reasons and is an exception from normal AArch64
+     disassembly scheme.  */
   AARCH64_OPND_QLF_S_4B,
+  AARCH64_OPND_QLF_S_2H,
 
   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
      register list; indicating register shape.
@@ -609,6 +613,7 @@ enum aarch64_insn_class
   cryptosm3,
   cryptosm4,
   dotproduct,
+  bfloat16,
 };
 
 /* Opcode enumerators.  */