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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2019-04-22 15:12:09 -0700 |
|---|---|---|
| committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-04-26 18:28:05 -0700 |
| commit | a45328b93bdd5399da8a9e56817e445cc2068edd (patch) | |
| tree | d611c35292391d313d6d99f80aa1495fdbdef046 /include | |
| parent | 45f0ab12d463cb3999a4286e679bdef05884b3a3 (diff) | |
| download | gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.zip gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.tar.gz gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.tar.bz2 | |
[MIPS] Add load-link, store-conditional paired instructions
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 01bb920..1f225b8 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> + Faraz Shahbazker <fshahbazker@wavecomp.com> + + * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. + (M_SCWP_AB, M_SCDP_AB): Likewise. + 2019-04-25 Maciej W. Rozycki <macro@linux-mips.org> * opcode/mips.h: Update comment for MIPS32 CODE20 operand. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 4309e1a..bc7deec 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1628,7 +1628,9 @@ enum M_LI_SS, M_LL_AB, M_LLD_AB, + M_LLDP_AB, M_LLE_AB, + M_LLWP_AB, M_LQ_AB, M_LW_AB, M_LWE_AB, @@ -1679,7 +1681,9 @@ enum M_SAAD_AB, M_SC_AB, M_SCD_AB, + M_SCDP_AB, M_SCE_AB, + M_SCWP_AB, M_SD_AB, M_SDC1_AB, M_SDC2_AB, |