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| author | Jim Wilson <jimw@sifive.com> | 2018-05-08 15:46:19 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-05-08 15:46:19 -0700 |
| commit | e6f372ba661bb0d8eec1e22a6dc1ad9937336e4d (patch) | |
| tree | 1e9fa44730d068196b581e511fe544517b1a7d6d /include | |
| parent | 7402fbcae1c282e27aafd5c5c90aca7eabbdf45c (diff) | |
| download | gdb-e6f372ba661bb0d8eec1e22a6dc1ad9937336e4d.zip gdb-e6f372ba661bb0d8eec1e22a6dc1ad9937336e4d.tar.gz gdb-e6f372ba661bb0d8eec1e22a6dc1ad9937336e4d.tar.bz2 | |
RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 704d1e9..5dceeb1 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2018-05-08 Jim Wilson <jimw@sifive.com> + + * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. + (MATCH_C_SRAI64, MASK_C_SRAI64): New. + (MATCH_C_SLLI64, MASK_C_SLLI64): New. + 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com> * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index f966fb6..60bd2f9 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -459,8 +459,12 @@ #define MASK_C_LUI 0xe003 #define MATCH_C_SRLI 0x8001 #define MASK_C_SRLI 0xec03 +#define MATCH_C_SRLI64 0x8001 +#define MASK_C_SRLI64 0xfc7f #define MATCH_C_SRAI 0x8401 #define MASK_C_SRAI 0xec03 +#define MATCH_C_SRAI64 0x8401 +#define MASK_C_SRAI64 0xfc7f #define MATCH_C_ANDI 0x8801 #define MASK_C_ANDI 0xec03 #define MATCH_C_SUB 0x8c01 @@ -483,6 +487,8 @@ #define MASK_C_BNEZ 0xe003 #define MATCH_C_SLLI 0x2 #define MASK_C_SLLI 0xe003 +#define MATCH_C_SLLI64 0x2 +#define MASK_C_SLLI64 0xf07f #define MATCH_C_FLDSP 0x2002 #define MASK_C_FLDSP 0xe003 #define MATCH_C_LWSP 0x4002 |