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| author | Nick Clifton <nickc@redhat.com> | 2018-03-28 09:44:45 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2018-03-28 09:44:45 +0100 |
| commit | c8d59609b1cf66eaff3c486e483f5e3d647c66ff (patch) | |
| tree | 66054d403bc11d2c064100c3a159a08a2005233c /include | |
| parent | 9c75b45645acb30c42f09b80cbaadbde391aa7b2 (diff) | |
| download | gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.zip gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.tar.gz gdb-c8d59609b1cf66eaff3c486e483f5e3d647c66ff.tar.bz2 | |
Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register.
PR 22988
opcode * opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_SVE_ADDR_R.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
instructions with only a base address register.
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * config/tc-aarch64.c (parse_operands): Add code to handle
AARCH64_OPN_SVE_ADDR_R.
* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
with an assumed XZR offset address register.
* testsuite/gas/aarch64/sve.d: Update expected disassembly.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 448c6e3..f7f4655 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2018-03-28 Nick Clifton <nickc@redhat.com> + + PR 22988 + * opcode/aarch64.h (enum aarch64_opnd): Add + AARCH64_OPND_SVE_ADDR_R. + 2018-03-21 H.J. Lu <hongjiu.lu@intel.com> * elf/common.h (DF_1_KMOD): New. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a94d779..16c41bf 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -272,6 +272,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ + AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ |