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| author | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:36:34 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:36:34 +0000 |
| commit | 795b8e6bf35ad70e7da086831ad01d4b0660ba2d (patch) | |
| tree | 5b813493203eae5edc27c2ce3fa38af106fd2a77 /include/xtensa-isa-internal.h | |
| parent | e3f1ad4fd2e99bd226f19f88c513f13f3434de44 (diff) | |
| download | gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.zip gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.tar.gz gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.tar.bz2 | |
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
Diffstat (limited to 'include/xtensa-isa-internal.h')
0 files changed, 0 insertions, 0 deletions