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author | Andrew Waterman <andrew@sifive.com> | 2017-02-22 21:23:05 -0800 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-02-24 09:24:58 -0800 |
commit | 742d14b39b384e822fd2218cf1803aef68a95d99 (patch) | |
tree | d7c858c08919446e5398dc2d4c5b1b6bcf8ec136 /include/opcode | |
parent | b0e4b369d519f9c604bddd6305e64dbb9f794256 (diff) | |
download | gdb-742d14b39b384e822fd2218cf1803aef68a95d99.zip gdb-742d14b39b384e822fd2218cf1803aef68a95d99.tar.gz gdb-742d14b39b384e822fd2218cf1803aef68a95d99.tar.bz2 |
Add new counter-enable CSRs
include/ChangeLog:
2017-02-22 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
(CSR_MCOUNTEREN): Likewise.
(scounteren): Declare register.
(mcounteren): Likewise.
Diffstat (limited to 'include/opcode')
-rw-r--r-- | include/opcode/riscv-opc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index dd58053..8f0f2bc 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -605,6 +605,7 @@ #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 @@ -617,6 +618,7 @@ #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -1095,6 +1097,7 @@ DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) @@ -1107,6 +1110,7 @@ DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) |