aboutsummaryrefslogtreecommitdiff
path: root/include/opcode
diff options
context:
space:
mode:
authorNick Clifton <nickc@redhat.com>2020-01-02 12:04:40 +0000
committerNick Clifton <nickc@redhat.com>2020-01-02 12:04:40 +0000
commitd73b58f4b1f193d2e58c0a1774e01561b16866b9 (patch)
treeed8b8a60b56dff1ff4c1f9e4d58441583d90fc53 /include/opcode
parenta7e3d08a26edefa411269636d7dcae7dd2736659 (diff)
downloadgdb-d73b58f4b1f193d2e58c0a1774e01561b16866b9.zip
gdb-d73b58f4b1f193d2e58c0a1774e01561b16866b9.tar.gz
gdb-d73b58f4b1f193d2e58c0a1774e01561b16866b9.tar.bz2
Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.
* opcode/s12z.h: Undef REG_Y.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/s12z.h24
1 files changed, 14 insertions, 10 deletions
diff --git a/include/opcode/s12z.h b/include/opcode/s12z.h
index 7e38ac5..3fd2dd0 100644
--- a/include/opcode/s12z.h
+++ b/include/opcode/s12z.h
@@ -2,25 +2,30 @@
#define S12Z_H
/* This byte is used to prefix instructions in "page 2" of the opcode
- space */
+ space. */
#define PAGE2_PREBYTE (0x1b)
struct reg
{
- char *name; /* The canonical name of the register */
- int bytes; /* its size, in bytes */
+ char *name; /* The canonical name of the register. */
+ int bytes; /* its size, in bytes. */
};
/* How many registers do we have. Actually there are only 13,
because CCL and CCH are the low and high bytes of CCW. But
for assemnbly / disassembly purposes they are considered
- distinct registers. */
+ distinct registers. */
#define S12Z_N_REGISTERS 15
extern const struct reg registers[S12Z_N_REGISTERS];
-enum {
+/* Solaris defines REG_Y in sys/regset.h; undef it here to avoid
+ breaking compilation when this target is enabled. */
+#undef REG_Y
+
+enum
+ {
REG_D2 = 0,
REG_D3,
REG_D4,
@@ -38,7 +43,7 @@ enum {
REG_CCW
};
-/* Any of the registers d0, d1, ... d7 */
+/* Any of the registers d0, d1, ... d7. */
#define REG_BIT_Dn \
((0x1U << REG_D2) | \
(0x1U << REG_D3) | \
@@ -49,23 +54,22 @@ enum {
(0x1U << REG_D0) | \
(0x1U << REG_D1))
-/* Any of the registers x, y or z */
+/* Any of the registers x, y or z. */
#define REG_BIT_XYS \
((0x1U << REG_X) | \
(0x1U << REG_Y) | \
(0x1U << REG_S))
-/* Any of the registers x, y, z or p */
+/* Any of the registers x, y, z or p. */
#define REG_BIT_XYSP \
((0x1U << REG_X) | \
(0x1U << REG_Y) | \
(0x1U << REG_S) | \
(0x1U << REG_P))
-/* The x register or the y register */
+/* The x register or the y register. */
#define REG_BIT_XY \
((0x1U << REG_X) | \
(0x1U << REG_Y))
-
#endif