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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2001-08-10 16:20:43 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2001-08-10 16:20:43 +0000 |
| commit | a58ec95a7edf6346fcf46acc0f66d368ab64d34e (patch) | |
| tree | 8e72995ce8b38b70c976460999cfd56f600fffa0 /include/opcode | |
| parent | fd969be2aa42916f03790f1be65350fea5fce896 (diff) | |
| download | gdb-a58ec95a7edf6346fcf46acc0f66d368ab64d34e.zip gdb-a58ec95a7edf6346fcf46acc0f66d368ab64d34e.tar.gz gdb-a58ec95a7edf6346fcf46acc0f66d368ab64d34e.tar.bz2 | |
* opcode/mips.h (INSN_GP32): Remove.
(OPCODE_IS_MEMBER): Remove gp32 parameter.
(M_MOVE): New macro identifier.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/mips.h | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 8fc11a3..23e6028 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -326,8 +326,6 @@ struct mips_opcode #define INSN_4100 0x00040000 /* Toshiba R3900 instruction. */ #define INSN_3900 0x00080000 -/* 32-bit code running on a ISA3+ CPU. */ -#define INSN_GP32 0x00100000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -369,15 +367,10 @@ struct mips_opcode /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. - The gp32 arg is set when you need to force 32-bit register usage on - a machine with 64-bit registers; see the documentation under -mgp32 - in the MIPS gas docs. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ - ((((insn)->membership & isa) != 0 \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1) \ - ) \ + to test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ @@ -508,6 +501,7 @@ enum M_LWR_A, M_LWR_AB, M_LWU_AB, + M_MOVE, M_MUL, M_MUL_I, M_MULO, |