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authorThiemo Seufer <ths@networkno.de>2001-08-16 19:24:33 +0000
committerThiemo Seufer <ths@networkno.de>2001-08-16 19:24:33 +0000
commit99c14723f3f437e55488c8819241d359414ec9d6 (patch)
treea2d0bdc6122e67dcf915754adb1f2bf637292921 /include/opcode
parent2cd8959083e24196760ddf35310c6c8d88ba00df (diff)
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Add support for MIPS R1[02]000 performance counter opcodes.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/mips.h6
2 files changed, 10 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b95cf1e..981de9e 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips.h (INSN_10000): Define.
+ (OPCODE_IS_MEMBER): Check for INSN_10000.
+
2001-08-10 Alan Modra <amodra@one.net.au>
* ppc.h: Revert 2001-08-08.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 23e6028..349d266 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -326,6 +326,8 @@ struct mips_opcode
#define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00080000
+/* MIPS R10000 instruction. */
+#define INSN_10000 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -375,7 +377,9 @@ struct mips_opcode
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
&& ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
+ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
+ || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
+ && ((insn)->membership & INSN_10000) != 0))
/* This is a list of macro expanded instructions.