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| author | Chris Demetriou <cgd@google.com> | 2002-03-16 03:09:19 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-03-16 03:09:19 +0000 |
| commit | 1f25f5d300a19ce6256f5d08ffe3c89dac61eca5 (patch) | |
| tree | e6c2be3e5e29f3440da505a84368b6f0db0fb385 /include/opcode | |
| parent | 376c9600197cb583397c4bf8a2cd49e23693bf6d (diff) | |
| download | gdb-1f25f5d300a19ce6256f5d08ffe3c89dac61eca5.zip gdb-1f25f5d300a19ce6256f5d08ffe3c89dac61eca5.tar.gz gdb-1f25f5d300a19ce6256f5d08ffe3c89dac61eca5.tar.bz2 | |
[ gas/ChangeLog ]
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mips3d" member.
(mips_opts): Initialize "ase_mips3d" member.
(file_ase_mips3d): New variable.
(CPU_HAS_MIPS3D): New macro.
(md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d
based on command line options and configuration defaults.
(macro_build, mips_ip): Accept MIPS-3D instructions if
mips_opts.ase_mips3d is set.
(OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option):
Add support for "-mips3d" and "-no-mips3d" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mips3d" and ".set nomips3d".
(mips_elf_final_processing): Add a comment indicating that a
MIPS-3D ASE ELF header flag should be set, when one exists.
* doc/as.texinfo: Document -mips3d and -no-mips3d options.
* doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set
nomips3d" directives.
[ gas/testsuite/ChangeLog ]
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mips3d.s: New file.
* gas/mips/mips64-mips3d.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mips3d" test.
[ include/opcode/ChangeLog ]
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
instructions.
(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
may be passed along with the ISA bitmask.
[ opcodes/ChangeLog ]
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add
comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
indicate that they should dissassemble all applicable
MIPS-specified ASEs.
* mips-opc.c: Add support for MIPS-3D instructions.
(M3D): New definition.
* mips-opc.c: Update copyright years.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 7 | ||||
| -rw-r--r-- | include/opcode/mips.h | 13 |
2 files changed, 16 insertions, 4 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9548338..f73a5a8 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D + instructions. + (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks + may be passed along with the ISA bitmask. + 2002-03-05 Paul Koning <pkoning@equallogic.com> * pdp11.h: Add format codes for float instruction formats. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1469e10..96c7a57 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -316,6 +316,11 @@ struct mips_opcode #define INSN_ISA32 0x00000200 #define INSN_ISA64 0x00000400 +/* Masks used for MIPS-defined ASEs. */ + +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00004000 + /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -367,10 +372,10 @@ struct mips_opcode #define CPU_MIPS64 64 #define CPU_SB1 12310201 /* octal 'SB', 01. */ -/* Test for membership in an ISA including chip specific ISAs. - INSN is pointer to an element of the opcode table; ISA is the - specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. */ +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ #define OPCODE_IS_MEMBER(insn, isa, cpu) \ (((insn)->membership & isa) != 0 \ |