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authorAndrew Burgess <andrew.burgess@embecosm.com>2016-06-02 14:03:23 +0100
committerNick Clifton <nickc@redhat.com>2016-06-02 14:03:23 +0100
commit4eb6f892502bad1ec4e1828d0140959bb004a3b6 (patch)
treeb1f2e98c1a8fde0077bc4831607528533b25a241 /include/opcode
parent5b6312fd20ef39f1531e37e7d2601c54d5658119 (diff)
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Add support for 48 and 64 bit ARC instructions.
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/arc.h26
1 files changed, 25 insertions, 1 deletions
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 444341a..b71c2f5 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -25,7 +25,7 @@
#define OPCODE_ARC_H
#ifndef MAX_INSN_ARGS
-#define MAX_INSN_ARGS 8
+#define MAX_INSN_ARGS 16
#endif
#ifndef MAX_INSN_FLGS
@@ -136,6 +136,30 @@ struct arc_opcode
unsigned char flags[MAX_INSN_FLGS + 1];
};
+/* Structure used to describe 48 and 64 bit instructions. */
+struct arc_long_opcode
+{
+ /* The base instruction is either 16 or 32 bits, and is described like a
+ normal instruction. */
+ struct arc_opcode base_opcode;
+
+ /* The template value for the 32-bit LIMM extension. Used by the
+ assembler and disassembler in the same way as the 'opcode' field of
+ 'struct arc_opcode'. */
+ unsigned limm_template;
+
+ /* The mask value for the 32-bit LIMM extension. Used by the
+ disassembler just like the 'mask' field in 'struct arc_opcode'. */
+ unsigned limm_mask;
+
+ /* Array of operand codes similar to the 'operands' array in 'struct
+ arc_opcode'. These operands are used to fill in the LIMM value. */
+ unsigned char operands[MAX_INSN_ARGS + 1];
+};
+
+extern const struct arc_long_opcode arc_long_opcodes[];
+extern const unsigned arc_num_long_opcodes;
+
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */