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authorThiemo Seufer <ths@networkno.de>2006-05-04 10:47:05 +0000
committerThiemo Seufer <ths@networkno.de>2006-05-04 10:47:05 +0000
commit39a7806daee10b8020ce7be18e54cab69c9e699f (patch)
treee0e709f3dc36ebd5135bd8a533c7f16a44ec5a3c /include/opcode
parent9578239d3edd0341cca6686bdf89ba9f5a1cd9f7 (diff)
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[ gas/testsuite/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/ChangeLog6
-rw-r--r--include/opcode/mips.h6
2 files changed, 11 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 1d398f6..b3ab82c 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2006-05-04 Thiemo Seufer <ths@mips.com>
+ Nigel Stephens <nigel@mips.com>
+ David Ung <davidu@mips.com>
+
+ * mips.h: Add INSN_SMARTMIPS define.
+
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 34ef26e..61601f8 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -485,7 +485,7 @@ struct mips_opcode
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
-#define INSN_ASE_MASK 0x0400f000
+#define INSN_ASE_MASK 0x0c00f000
/* DSP ASE */
#define INSN_DSP 0x00001000
@@ -518,9 +518,13 @@ struct mips_opcode
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+
/* MT ASE */
#define INSN_MT 0x04000000
+/* SmartMIPS ASE. */
+#define INSN_SMARTMIPS 0x08000000
+
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_UNKNOWN 0 /* Gas internal use. */