aboutsummaryrefslogtreecommitdiff
path: root/include/opcode
diff options
context:
space:
mode:
authorAlan Modra <amodra@gmail.com>2016-12-21 19:13:52 +1030
committerAlan Modra <amodra@gmail.com>2016-12-21 19:18:46 +1030
commit4e25adb3956f880efc28bfebabe79be7338b413f (patch)
tree9e8b41dbf37bac5ab3c6c78abdd26ff6c59019fc /include/opcode
parent9962fe293d16e1e1e4d05154e751fc7576226954 (diff)
downloadgdb-4e25adb3956f880efc28bfebabe79be7338b413f.zip
gdb-4e25adb3956f880efc28bfebabe79be7338b413f.tar.gz
gdb-4e25adb3956f880efc28bfebabe79be7338b413f.tar.bz2
Remove high bit set characters
gas/ * doc/c-lm32.texi: Fix chars with high bit set. * testsuite/gas/bfin/vector2.s: Likewise. gold/ * arm.cc: Fix comment chars with high bit set. include/ * coff/pe.h: Fix comment chars with high bit set. * opcode/xgate.h: Likewise. ld/ * testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/xgate.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/opcode/xgate.h b/include/opcode/xgate.h
index 737c0d9..ad4dbb1 100644
--- a/include/opcode/xgate.h
+++ b/include/opcode/xgate.h
@@ -29,14 +29,14 @@
#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
/* Access Detail Notation
- V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
- P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
- r — 8-bit data read: lasts for at least one RISC core cycle
- R — 16-bit data read: lasts for at least one RISC core cycle
- w — 8-bit data write: lasts for at least one RISC core cycle
- W — 16-bit data write: lasts for at least one RISC core cycle
- A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
- f — Free cycle: no read or write, lasts for one RISC core cycles. */
+ V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
+ P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
+ r - 8-bit data read: lasts for at least one RISC core cycle
+ R - 16-bit data read: lasts for at least one RISC core cycle
+ w - 8-bit data write: lasts for at least one RISC core cycle
+ W - 16-bit data write: lasts for at least one RISC core cycle
+ A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
+ f - Free cycle: no read or write, lasts for one RISC core cycles. */
#define XGATE_CYCLE_V 0x01
#define XGATE_CYCLE_P 0x02
#define XGATE_CYCLE_r 0x04