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author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:56:57 +0100 |
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committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:56:57 +0100 |
commit | e950b3453948830c5ce9c2f70d114d0b38a4b4ac (patch) | |
tree | 86d0ac10f2bf7783666d4059419b606d3fbb5a38 /include/opcode | |
parent | 98907a704908c5877d929c57b2ddb2e5f899d9a9 (diff) | |
download | gdb-e950b3453948830c5ce9c2f70d114d0b38a4b4ac.zip gdb-e950b3453948830c5ce9c2f70d114d0b38a4b4ac.tar.gz gdb-e950b3453948830c5ce9c2f70d114d0b38a4b4ac.tar.bz2 |
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
Diffstat (limited to 'include/opcode')
-rw-r--r-- | include/opcode/aarch64.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 837d6bd..36e95b4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -200,6 +200,7 @@ enum aarch64_opnd AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ + AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ @@ -289,6 +290,11 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ + AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ + AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ + AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ + AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ + AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ @@ -300,6 +306,18 @@ enum aarch64_opnd AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ + AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ + AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ + AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ + AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ + AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ + AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ + AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ + AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ + AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ + AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ + AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ + AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ @@ -1065,6 +1083,9 @@ aarch64_get_operand_name (enum aarch64_opnd); extern const char * aarch64_get_operand_desc (enum aarch64_opnd); +extern bfd_boolean +aarch64_sve_dupm_mov_immediate_p (uint64_t, int); + #ifdef DEBUG_AARCH64 extern int debug_dump; |