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authorRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:58:22 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:58:22 +0100
commit116b60193779ac65a29fb3688b753527980cb3e7 (patch)
tree40eaa4854176b9fcdf985ae996869ed62f2225b3 /include/opcode
parent047cd301d40288d13e44f3322541ac28ebe06078 (diff)
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[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how an index into an aarch64_opnd_qualifier_seq_t is represented in the instruction encoding. Other instructions usually use flags for this information, but (a) we're running out of those and (b) the iclass would otherwise be unused for SVE. include/ * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc) (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred) (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New aarch64_insn_classes. opcodes/ * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. * aarch64-asm.c (aarch64_get_variant): New function. (aarch64_encode_variant_using_iclass): Likewise. (aarch64_opcode_encode): Call it. * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. (aarch64_opcode_decode): Call it.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/aarch64.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8d3fb21..01e6b2c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -485,6 +485,18 @@ enum aarch64_insn_class
movewide,
pcreladdr,
ic_system,
+ sve_cpy,
+ sve_index,
+ sve_limm,
+ sve_misc,
+ sve_movprfx,
+ sve_pred_zm,
+ sve_shift_pred,
+ sve_shift_unpred,
+ sve_size_bhs,
+ sve_size_bhsd,
+ sve_size_hsd,
+ sve_size_sd,
testbranch,
};