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| author | Cooper Qu <cooper.qu@linux.alibaba.com> | 2020-09-11 23:58:11 +0800 |
|---|---|---|
| committer | Lifang Xia <xlf194833_xia@alibaba-inc.com> | 2020-09-12 00:56:01 +0800 |
| commit | 548f5275787a2328b5c1ea041e13a53e67d4accb (patch) | |
| tree | fc4badb0bb54af3e4ce70589a97af6f63660d2d6 /include/opcode | |
| parent | 9cdc5bacddc3776a455cc918e034b01dfb31c75b (diff) | |
| download | gdb-548f5275787a2328b5c1ea041e13a53e67d4accb.zip gdb-548f5275787a2328b5c1ea041e13a53e67d4accb.tar.gz gdb-548f5275787a2328b5c1ea041e13a53e67d4accb.tar.bz2 | |
CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.
The previous patch missed one modification.
Following is the error message:
gas/config/tc-csky.c:806:5: error: 'CSKY_ARCH_804' undeclared here
(not in a function); did you mean 'CSKY_ARCH_807'?
include/
* opcode/csky.h (CSKYV1_ISA_E1): Convert to bfd_uint64_t type.
(CSKYV2_ISA_E1): Likewise.
(CSKYV2_ISA_1E2): Likewise.
(CSKYV2_ISA_2E3): Likewise.
(CSKYV2_ISA_3E7): Likewise.
(CSKYV2_ISA_7E10): Likewise.
(CSKYV2_ISA_3E3R1): Likewise.
(CSKYV2_ISA_3E3R2): Likewise.
(CSKYV2_ISA_10E60): Likewise.
(CSKYV2_ISA_3E3R3): Likewise.
(CSKY_ISA_TRUST): Likewise.
(CSKY_ISA_CACHE): Likewise.
(CSKY_ISA_NVIC): Likewise.
(CSKY_ISA_CP): Likewise.
(CSKY_ISA_MP): Likewise.
(CSKY_ISA_MP_1E2): Likewise.
(CSKY_ISA_JAVA): Likewise.
(CSKY_ISA_MAC): Likewise.
(CSKY_ISA_MAC_DSP): Likewise.
(CSKY_ISA_DSP): Likewise.
(CSKY_ISA_DSP_1E2): Likewise.
(CSKY_ISA_DSP_ENHANCE): Likewise.
(CSKY_ISA_DSPE60): Likewise.
(CSKY_ISA_FLOAT_E1): Likewise.
(CSKY_ISA_FLOAT_1E2): Likewise.
(CSKY_ISA_FLOAT_1E3): Likewise.
(CSKY_ISA_FLOAT_3E4): Likewise.
(CSKY_ISA_FLOAT_7E60): Likewise.
(CSKY_ISA_VDSP): Likewise.
(CSKY_ISA_VDSP_2): Likewise.
(CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/csky.h | 67 |
1 files changed, 36 insertions, 31 deletions
diff --git a/include/opcode/csky.h b/include/opcode/csky.h index 717e8a9..1ff9dfa 100644 --- a/include/opcode/csky.h +++ b/include/opcode/csky.h @@ -22,46 +22,46 @@ #include "dis-asm.h" /* The following bitmasks control instruction set architecture. */ -#define CSKYV1_ISA_E1 (1L << 0) -#define CSKYV2_ISA_E1 (1L << 1) -#define CSKYV2_ISA_1E2 (1L << 2) -#define CSKYV2_ISA_2E3 (1L << 3) -#define CSKYV2_ISA_3E7 (1L << 4) -#define CSKYV2_ISA_7E10 (1L << 5) -#define CSKYV2_ISA_3E3R1 (1L << 6) -#define CSKYV2_ISA_3E3R2 (1L << 7) -#define CSKYV2_ISA_10E60 (1L << 8) -#define CSKYV2_ISA_3E3R3 (1L << 9) - -#define CSKY_ISA_TRUST (1L << 11) -#define CSKY_ISA_CACHE (1L << 12) -#define CSKY_ISA_NVIC (1L << 13) -#define CSKY_ISA_CP (1L << 14) -#define CSKY_ISA_MP (1L << 15) -#define CSKY_ISA_MP_1E2 (1L << 16) -#define CSKY_ISA_JAVA (1L << 17) -#define CSKY_ISA_MAC (1L << 18) -#define CSKY_ISA_MAC_DSP (1L << 19) +#define CSKYV1_ISA_E1 ((bfd_uint64_t)1 << 0) +#define CSKYV2_ISA_E1 ((bfd_uint64_t)1 << 1) +#define CSKYV2_ISA_1E2 ((bfd_uint64_t)1 << 2) +#define CSKYV2_ISA_2E3 ((bfd_uint64_t)1 << 3) +#define CSKYV2_ISA_3E7 ((bfd_uint64_t)1 << 4) +#define CSKYV2_ISA_7E10 ((bfd_uint64_t)1 << 5) +#define CSKYV2_ISA_3E3R1 ((bfd_uint64_t)1 << 6) +#define CSKYV2_ISA_3E3R2 ((bfd_uint64_t)1 << 7) +#define CSKYV2_ISA_10E60 ((bfd_uint64_t)1 << 8) +#define CSKYV2_ISA_3E3R3 ((bfd_uint64_t)1 << 9) + +#define CSKY_ISA_TRUST ((bfd_uint64_t)1 << 11) +#define CSKY_ISA_CACHE ((bfd_uint64_t)1 << 12) +#define CSKY_ISA_NVIC ((bfd_uint64_t)1 << 13) +#define CSKY_ISA_CP ((bfd_uint64_t)1 << 14) +#define CSKY_ISA_MP ((bfd_uint64_t)1 << 15) +#define CSKY_ISA_MP_1E2 ((bfd_uint64_t)1 << 16) +#define CSKY_ISA_JAVA ((bfd_uint64_t)1 << 17) +#define CSKY_ISA_MAC ((bfd_uint64_t)1 << 18) +#define CSKY_ISA_MAC_DSP ((bfd_uint64_t)1 << 19) /* Base ISA for csky v1 and v2. */ -#define CSKY_ISA_DSP (1L << 20) -#define CSKY_ISA_DSP_1E2 (1L << 21) -#define CSKY_ISA_DSP_ENHANCE (1L << 22) -#define CSKY_ISA_DSPE60 (1L << 23) +#define CSKY_ISA_DSP ((bfd_uint64_t)1 << 20) +#define CSKY_ISA_DSP_1E2 ((bfd_uint64_t)1 << 21) +#define CSKY_ISA_DSP_ENHANCE ((bfd_uint64_t)1 << 22) +#define CSKY_ISA_DSPE60 ((bfd_uint64_t)1 << 23) /* Base float instruction (803f & 810f). */ -#define CSKY_ISA_FLOAT_E1 (1L << 25) +#define CSKY_ISA_FLOAT_E1 ((bfd_uint64_t)1 << 25) /* M_FLOAT support (810f). */ -#define CSKY_ISA_FLOAT_1E2 (1L << 26) +#define CSKY_ISA_FLOAT_1E2 ((bfd_uint64_t)1 << 26) /* 803 support (803f). */ -#define CSKY_ISA_FLOAT_1E3 (1L << 27) +#define CSKY_ISA_FLOAT_1E3 ((bfd_uint64_t)1 << 27) /* 807 support (803f & 807f). */ -#define CSKY_ISA_FLOAT_3E4 (1L << 28) +#define CSKY_ISA_FLOAT_3E4 ((bfd_uint64_t)1 << 28) /* 860 support. */ -#define CSKY_ISA_FLOAT_7E60 (1LL << 36) +#define CSKY_ISA_FLOAT_7E60 ((bfd_uint64_t)1 << 36) /* Vector DSP support. */ -#define CSKY_ISA_VDSP (1L << 29) -#define CSKY_ISA_VDSP_2 (1L << 30) +#define CSKY_ISA_VDSP ((bfd_uint64_t)1 << 29) +#define CSKY_ISA_VDSP_2 ((bfd_uint64_t)1 << 30) /* The following bitmasks control cpu architecture for CSKY. */ #define CSKY_ABI_V1 (1 << 28) @@ -74,9 +74,14 @@ #define CSKY_ARCH_801 0xa #define CSKY_ARCH_802 0x10 #define CSKY_ARCH_803 0x9 +/* 804 use the same arch flag as 803 yet. */ +#define CSKY_ARCH_804 0x9 +#define CSKY_ARCH_805 0x11 #define CSKY_ARCH_807 0x6 #define CSKY_ARCH_810 0x8 #define CSKY_ARCH_860 0xb +/* 800 is a special arch supporting all instructions for ABIV2. */ +#define CSKY_ARCH_800 0x1f #define CSKY_ARCH_MAC (1 << 15) #define CSKY_ARCH_DSP (1 << 14) |