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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:50:43 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:50:43 +0000 |
| commit | 27c5c572c911ec2f77bab953586870919db15a29 (patch) | |
| tree | 3707c6f2cb9bb03b201d4ad70e28086b9830726b /include/opcode | |
| parent | e76ff5abe375e1e7535f7827db01bce70bc9710d (diff) | |
| download | gdb-27c5c572c911ec2f77bab953586870919db15a29.zip gdb-27c5c572c911ec2f77bab953586870919db15a29.tar.gz gdb-27c5c572c911ec2f77bab953586870919db15a29.tar.bz2 | |
include/opcode/
* mips.h: Document "+i".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
(mips_ip, mips16_ip): Handle "+i".
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 9 |
2 files changed, 10 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f132fd3..b2b718c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,5 +1,9 @@ 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * mips.h: Document "+i". + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 4dfec6c..d25b136 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -379,6 +379,7 @@ struct mips_opcode "<" 5 bit shift amount (OP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) "a" 26 bit target address (OP_*_TARGET) + "+i" likewise, but flips bit 0 "b" 5 bit base register (OP_*_RS) "c" 10 bit breakpoint code (OP_*_CODE) "d" 5 bit destination register specifier (OP_*_RD) @@ -539,7 +540,7 @@ struct mips_opcode following), for quick reference when adding more: "1234" "ABCEFGHIJPQSXZ" - "abcjpstxz" + "abcijpstxz" */ /* These are the bits which may be set in the pinfo field of an @@ -1383,6 +1384,7 @@ extern int bfd_mips_num_opcodes; "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) "a" 26 bit jump address + "i" likewise, but flips bit 0 "e" 11 bit extension value "l" register list for entry instruction "L" register list for exit instruction @@ -1741,6 +1743,7 @@ extern const int bfd_mips16_num_opcodes; "|" 4-bit trap code (MICROMIPSOP_*_TRAP) "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) "a" 26-bit target address (MICROMIPSOP_*_TARGET) + "+i" likewise, but flips bit 0 "b" 5-bit base register (MICROMIPSOP_*_RS) "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) @@ -1846,10 +1849,10 @@ extern const int bfd_mips16_num_opcodes; Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "j" "" - "ABCEFGHI" "" + "ABCEFGHI" + "ij" Extension character sequences used so far ("m" followed by the following), for quick reference when adding more: |