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| author | Cooper Qu <cooper.qu@linux.alibaba.com> | 2020-08-24 20:13:47 +0800 |
|---|---|---|
| committer | Lifang Xia <lifang_xia@c-sky.com> | 2020-08-24 20:27:07 +0800 |
| commit | 531c73a37bb4477f8337bb9dddc36d552ee76056 (patch) | |
| tree | e9602367da318d2f52ee872304c8fe3f95d6dc60 /include/opcode | |
| parent | f1a9fbd995b8997b7ed7e8e6a83129e923400a58 (diff) | |
| download | gdb-531c73a37bb4477f8337bb9dddc36d552ee76056.zip gdb-531c73a37bb4477f8337bb9dddc36d552ee76056.tar.gz gdb-531c73a37bb4477f8337bb9dddc36d552ee76056.tar.bz2 | |
CSKY: Add new arch CK860.
bfd/
* bfd-in2.h (bfd_mach_ck860): New.
* cpu-csky.c (arch_info_struct): Add item for CK860.
gas/
* config/tc-csky.c (csky_archs): Add item for CK860,
change ck810 and ck807's arch_flag.
(csky_cpus): Add item for CK860.
(md_begin): Enable DSP for CK810 and CK807 by default.
(md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
* gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
to 'sync'.
* gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d: New.
* gas/testsuite/gas/csky/cskyv2_ck860.s: New.
* gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
to plsli.16.
* gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
include/
* opcode/csky.h (CSKYV2_ISA_10E60): New.
(CSKY_ARCH_860): New.
opcode/
* csky-dis.c (csky_find_inst_info): Skip CK860's instructions
in other CPUs to speed up disassembling.
* csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
Change plsli.u16 to plsli.16, change sync's operand format.
Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/csky.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/csky.h b/include/opcode/csky.h index 9b9dcc3..098bdc9 100644 --- a/include/opcode/csky.h +++ b/include/opcode/csky.h @@ -30,6 +30,7 @@ #define CSKYV2_ISA_7E10 (1 << 5) #define CSKYV2_ISA_3E3R1 (1 << 6) #define CSKYV2_ISA_3E3R2 (1 << 7) +#define CSKYV2_ISA_10E60 (1 << 8) #define CSKY_ISA_TRUST (1 << 11) #define CSKY_ISA_CACHE (1 << 12) @@ -70,6 +71,7 @@ #define CSKY_ARCH_803 0x9 #define CSKY_ARCH_807 0x6 #define CSKY_ARCH_810 0x8 +#define CSKY_ARCH_860 0xb #define CSKY_ARCH_MAC (1 << 15) #define CSKY_ARCH_DSP (1 << 14) |