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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:55 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:55 +0000 |
| commit | fa7616a4c7661cf786f3eaa9282072ca5dd8099c (patch) | |
| tree | 11ef2eb4ec10903834cb68365334d7a26b77c1b0 /include/opcode | |
| parent | 7c0de7419bd4f1b4aa0bdb3c15b03615dbe3959a (diff) | |
| download | gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.zip gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.tar.gz gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.tar.bz2 | |
include/opcode/
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 9 |
2 files changed, 6 insertions, 7 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b927a2c..c3d05fa 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove documentation of "+D" and "+T". + 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 68cd9b6..7ad60cb 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -448,8 +448,6 @@ struct mips_opcode "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. Macro instructions: "A" General 32 bit expression @@ -489,7 +487,6 @@ struct mips_opcode "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) @@ -543,7 +540,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234" - "ABCDEFGHIJPQSTXZ" + "ABCEFGHIJPQSXZ" "abcjpstxz" */ @@ -1816,8 +1813,6 @@ extern const int bfd_mips16_num_opcodes; "E" 5-bit target register (MICROMIPSOP_*_RT) "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - "+D" combined source register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only Macro instructions: "A" general 32 bit expression @@ -1859,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes; following), for quick reference when adding more: "j" "" - "ABCDEFGHI" + "ABCEFGHI" "" Extension character sequences used so far ("m" followed by the |