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| author | Jan Beulich <jbeulich@novell.com> | 2005-07-27 07:04:31 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2005-07-27 07:04:31 +0000 |
| commit | 8b5328ac50681bbb28f0f2b414a33e0fad079288 (patch) | |
| tree | 23ce950054a6214b10806a360d4b73121c0ddacf /include/opcode | |
| parent | a33d77bc5f66024ba9124be9642ddc0c06714139 (diff) | |
| download | gdb-8b5328ac50681bbb28f0f2b414a33e0fad079288.zip gdb-8b5328ac50681bbb28f0f2b414a33e0fad079288.tar.gz gdb-8b5328ac50681bbb28f0f2b414a33e0fad079288.tar.bz2 | |
include/opcode/
2005-07-27 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add comment to movd. Use LongMem for all
movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
Add movq-s as 64-bit variants of movd-s.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/i386.h | 20 |
2 files changed, 20 insertions, 6 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 7f515c6..1a05c70 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,9 @@ +2005-07-27 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Add comment to movd. Use LongMem for all + movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. + Add movq-s as 64-bit variants of movd-s. + 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> * hppa.h: Fix punctuation in comment. diff --git a/include/opcode/i386.h b/include/opcode/i386.h index c7f2b45..59b5e3c 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -995,16 +995,24 @@ static const template i386_optab[] = /* MMX/SSE2 instructions. */ {"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, +/* These really shouldn't allow for Reg64 (movq is the right mnemonic for + copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's + spec). AMD's spec, having been in existence for much longer, failed to + recognize that and specified movd for 32- and 64-bit operations. */ {"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, {"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } }, /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ -{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } }, +{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movq", 2, 0x0f6e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, +{"movq", 2, 0x660f6e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, +{"movq", 2, 0x660f7e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, /* We put the 64bit displacement first and we only mark constants larger than 32bit as Disp64. */ {"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } }, |