* hppa.h: Add gfw and gfr to the opcode table.

1 files changed, 25 insertions, 18 deletions

diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h
index 7a5ccb2..47470e1 100644
--- a/include/opcode/hppa.h
+++ b/include/opcode/hppa.h
@@ -67,7 +67,7 @@ struct pa_opcode
 
 	'  "#$%    *+- ./   3      :; =  @'
 	' B         L N            [\] _'
-	'    e gh   lm   qr      yz{|} '
+	'    e gh   lm   qr        { } '
 
    Here are all the characters:
 
@@ -76,9 +76,10 @@ struct pa_opcode
 	'abcdefghijklmnopqrstuvwxyz{|}~'
 
 Kinds of operands:
-   x    register field at 15.
-   b    register field at 10.
-   t    register field at 31.
+   x    integer register field at 15.
+   b    integer register field at 10.
+   t    integer register field at 31.
+   y    floating point register field at 31
    5    5 bit immediate at 15.
    s    2 bit space specifier at 17.
    S    3 bit space specifier at 18.
@@ -98,7 +99,8 @@ Kinds of operands:
    k    21 bit immediate value at 31
    n	nullification for branch instructions
    w    12 bit branch displacement
-   W    17 bit branch displacement
+   W    17 bit branch displacement (PC relative)
+   z    17 bit branch displacement (just a number, not an address)
 
 Also these:
 
@@ -140,6 +142,7 @@ Also these:
    Q	5 bit immediate value at 10 (a bit position specified in
 	the bb instruction. It's the same as r above, except the
         value is in a different location)
+   |	shift/extract/deposit conditions when used in a conditional branch
 
 And these (PJH) for PA-89 F.P. registers and instructions:
 
@@ -235,10 +238,10 @@ static const struct pa_opcode pa_opcodes[] =
 { "blr",	0xe8004000, 0xfc00e001, "nx,b", NORMAL},
 { "bv",		0xe800c000, 0xfc00e001, "nx(b)", NORMAL},
 { "bv",		0xe800c000, 0xfc00e001, "n(b)", NORMAL},
-{ "be",		0xe0000000, 0xfc000000, "nW(S,b)", NORMAL},
-{ "ble",	0xe4000000, 0xfc000000, "nW(S,b)", NORMAL},
-{ "movb",	0xc8000000, 0xfc000000, ">nx,b,w", CONDITIONAL},
-{ "movib",	0xcc000000, 0xfc000000, ">n5,b,w", CONDITIONAL},
+{ "be",		0xe0000000, 0xfc000000, "nz(S,b)", NORMAL},
+{ "ble",	0xe4000000, 0xfc000000, "nz(S,b)", NORMAL},
+{ "movb",	0xc8000000, 0xfc000000, "|nx,b,w", CONDITIONAL},
+{ "movib",	0xcc000000, 0xfc000000, "|n5,b,w", CONDITIONAL},
 { "combt",	0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
 { "combf",	0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
 { "comibt",	0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
@@ -362,25 +365,29 @@ static const struct pa_opcode pa_opcodes[] =
 { "fice",       0x040002c0, 0xfc003fdf, "Zx(s,b)"},
 { "fice",       0x040002c0, 0xfc003fdf, "Zx(b)"},
 { "diag",       0x14000000, 0xfc000000, "D"},
+{ "gfw",	0x04001680, 0xfc003fdf, "Zx(s,b)"},
+{ "gfw",	0x04001680, 0xfc003fdf, "Zx(b)"},
+{ "gfr",	0x04001a80, 0xfc003fdf, "Zx(s,b)"},
+{ "gfr",	0x04001a80, 0xfc003fdf, "Zx(b)"},
 
 /* Floating Point Coprocessor Instructions */
   
 { "fldwx",      0x24000000, 0xfc001f80, "cx(s,b),v"},
 { "fldwx",      0x24000000, 0xfc001f80, "cx(b),v"},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),t"},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cx(b),t"},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),y"},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cx(b),y"},
 { "fstwx",      0x24000200, 0xfc001fc0, "cv,x(s,b)"},
 { "fstwx",      0x24000200, 0xfc001fc0, "cv,x(b)"},
-{ "fstdx",      0x2c000200, 0xfc001fc0, "ct,x(s,b)"},
-{ "fstdx",      0x2c000200, 0xfc001fc0, "ct,x(b)"},
+{ "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(s,b)"},
+{ "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(b)"},
 { "fldws",      0x24001000, 0xfc001f80, "C5(s,b),v"},
 { "fldws",      0x24001000, 0xfc001f80, "C5(b),v"},
-{ "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),t"},
-{ "fldds",      0x2c001000, 0xfc001fc0, "C5(b),t"},
+{ "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),y"},
+{ "fldds",      0x2c001000, 0xfc001fc0, "C5(b),y"},
 { "fstws",      0x24001200, 0xfc001f80, "Cv,5(s,b)"},
-{ "fstws",      0x24001200, 0xfc001f80, "Ct,5(b)"},
-{ "fstds",      0x2c001200, 0xfc001fc0, "Ct,5(s,b)"},
-{ "fstds",      0x2c001200, 0xfc001fc0, "Ct,5(b)"},
+{ "fstws",      0x24001200, 0xfc001f80, "Cy,5(b)"},
+{ "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(s,b)"},
+{ "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(b)"},
 { "fadd",       0x30000600, 0xfc00e7e0, "FE,X,v"},
 { "fadd",       0x38000600, 0xfc00e720, "IJ,K,v"},
 { "fsub",       0x30002600, 0xfc00e7e0, "FE,X,v"},