arc/opcodes: Use flag operand class to handle multiple flag matches

When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled.  For example:

    adc.n.eq r0,r0,r2

Will assemble without error, yet, upon disassembly, the instruction will
actually be:

    adc.c r0,r0,r2

In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match.  Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.

To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used.  Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags.  However, at present, the class type is never used.  The current
values identify the type of instruction that the flag will be used in,
but this is not required information.

Instead, this commit discards the old flag classes, and introduces 3 new
classes.  The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class.  The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.

The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction.  The
"at most" one means that no flags being present is fine.

The class F_FLAG_REQUIRED is not currently used, but will be soon.  With
this class, exactly one of the flags from this class must be present in
the instruction.  If the flag class contains a single flag, then of
course that flag must be present.  However, if the flag class contained
two or more, then one, and only one of them must be present.

gas/ChangeLog:

	* config/tc-arc.c (find_opcode_match): Move lnflg, and i
	declarations to start of block.  Reset code on all flags before
	attempting to match them.  Handle multiple hits on the same flag.
	Handle flag class.
	* testsuite/gas/arc/asm-errors.d: New file.
	* testsuite/gas/arc/asm-errors.err: New file.
	* testsuite/gas/arc/asm-errors.s: New file.

include/ChangeLog:

	* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
	new classes instead.

opcodes/ChangeLog:

	* arc-opc.c (arc_flag_classes): Convert all flag classes to use
	the new class enum values.

1 files changed, 9 insertions, 9 deletions

diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 85ea735..3310c10 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -72,15 +72,15 @@ typedef enum
 /* Flags class.  */
 typedef enum
   {
-    FNONE,
-    CND,  /* Conditional flags.  */
-    WBM,  /* Write-back modes.  */
-    FLG,  /* F Flag.  */
-    SBP,  /* Static branch prediction.  */
-    DLY,  /* Delay slot.  */
-    DIF,  /* Bypass caches.  */
-    SGX,  /* Sign extend modes.  */
-    SZM   /* Data size modes.  */
+    F_CLASS_NONE,
+
+    /* At most one flag from the set of flags can appear in the
+       instruction.  */
+    F_CLASS_OPTIONAL,
+
+    /* Exactly one from from the set of flags must appear in the
+       instruction.  */
+    F_CLASS_REQUIRED,
   } flag_class_t;
 
 /* The opcode table is an array of struct arc_opcode.  */