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author | Trevor Saunders <tbsaunde+binutils@tbsaunde.org> | 2016-05-29 04:29:22 -0400 |
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committer | Trevor Saunders <tbsaunde+binutils@tbsaunde.org> | 2016-06-01 21:26:32 -0400 |
commit | 1fe0971e41a4097610862acabf54a896695fe834 (patch) | |
tree | 28a39e6d20644048ad87c57f257e8ec81db4cb4e /include/opcode | |
parent | 814f1489e9d1d92a30d94d69a0066addcc564bd2 (diff) | |
download | gdb-1fe0971e41a4097610862acabf54a896695fe834.zip gdb-1fe0971e41a4097610862acabf54a896695fe834.tar.gz gdb-1fe0971e41a4097610862acabf54a896695fe834.tar.bz2 |
add more extern C
opcodes/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* nds32-asm.h: Add extern "C".
* sh-opc.h: Likewise.
bfd/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* elf32-hppa.h: Add extern "C".
* elf32-nds32.h: Likewise.
* elf32-tic6x.h: Likewise.
include/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* elf/mips.h: Likewise.
* elf/sh.h: Likewise.
* opcode/d10v.h: Likewise.
* opcode/d30v.h: Likewise.
* opcode/ia64.h: Likewise.
* opcode/mips.h: Likewise.
* opcode/ppc.h: Likewise.
* opcode/sparc.h: Likewise.
* opcode/tic6x.h: Likewise.
* opcode/v850.h: Likewise.
Diffstat (limited to 'include/opcode')
-rw-r--r-- | include/opcode/d10v.h | 8 | ||||
-rw-r--r-- | include/opcode/d30v.h | 8 | ||||
-rw-r--r-- | include/opcode/ia64.h | 7 | ||||
-rw-r--r-- | include/opcode/mips.h | 8 | ||||
-rw-r--r-- | include/opcode/ppc.h | 8 | ||||
-rw-r--r-- | include/opcode/sparc.h | 7 | ||||
-rw-r--r-- | include/opcode/tic6x.h | 8 | ||||
-rw-r--r-- | include/opcode/v850.h | 8 |
8 files changed, 62 insertions, 0 deletions
diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h index 95aaf88..a468e58 100644 --- a/include/opcode/d10v.h +++ b/include/opcode/d10v.h @@ -22,6 +22,10 @@ #ifndef D10V_H #define D10V_H +#ifdef __cplusplus +extern "C" { +#endif + /* Format Specifier */ #define FM00 0 #define FM01 0x40000000 @@ -205,4 +209,8 @@ int d10v_reg_name_cnt (void); /* by setting high bits to indicate type */ #define REGISTER_MASK 0xFF +#ifdef __cplusplus +} +#endif + #endif /* D10V_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index 48aa1f1..910d155 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -22,6 +22,10 @@ #ifndef D30V_H #define D30V_H +#ifdef __cplusplus +extern "C" { +#endif + #define NOP 0x00F00000 /* Structure to hold information about predefined registers. */ @@ -284,4 +288,8 @@ struct d30v_insn /* by setting high bits to indicate type */ #define REGISTER_MASK 0xFF +#ifdef __cplusplus +} +#endif + #endif /* D30V_H */ diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h index 0995995..2463f5a 100644 --- a/include/opcode/ia64.h +++ b/include/opcode/ia64.h @@ -25,6 +25,9 @@ #include "bfd.h" +#ifdef __cplusplus +extern "C" { +#endif typedef BFD_HOST_U_64_BIT ia64_insn; @@ -418,4 +421,8 @@ extern const struct ia64_dependency *ia64_find_dependency (int); in bfd/cpu-ia64-opc.c: */ extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; +#ifdef __cplusplus +} +#endif + #endif /* opcode_ia64_h */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 0af3ed5..b1d4ef6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -25,6 +25,10 @@ #include "bfd.h" +#ifdef __cplusplus +extern "C" { +#endif + /* These are bit masks and shift counts to use to access the various fields of an instruction. To retrieve the X field of an instruction, use the expression @@ -2284,4 +2288,8 @@ extern const int bfd_micromips_num_opcodes; Used to implement -mfix-loongson2f. */ #define LOONGSON2F_NOP_INSN 0x00200825 +#ifdef __cplusplus +} +#endif + #endif /* _MIPS_H_ */ diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index df985eb..628a7a1 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -24,6 +24,10 @@ #include "bfd_stdint.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef uint64_t ppc_cpu_t; /* The opcode table is an array of struct powerpc_opcode. */ @@ -437,4 +441,8 @@ ppc_optional_operand_value (const struct powerpc_operand *operand) return 0; } +#ifdef __cplusplus +} +#endif + #endif /* PPC_H */ diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index 6eaa8ba..ff88092 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -21,6 +21,10 @@ #include "ansidecl.h" +#ifdef __cplusplus +extern "C" { +#endif + /* The SPARC opcode table (and other related data) is defined in the opcodes library in sparc-opc.c. If you change anything here, make sure you fix up that file, and vice versa. */ @@ -295,3 +299,6 @@ extern const char *sparc_decode_sparclet_cpreg (int); comment-column: 0 End: */ +#ifdef __cplusplus +} +#endif diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h index a45871a..3a9a63a 100644 --- a/include/opcode/tic6x.h +++ b/include/opcode/tic6x.h @@ -22,6 +22,10 @@ #include "bfd.h" #include "symcat.h" +#ifdef __cplusplus +extern "C" { +#endif + /* A field in an instruction format. The names are based on those used in the architecture manuals. */ typedef enum @@ -715,4 +719,8 @@ typedef struct bfd_boolean p_bits[14]; } tic6x_fetch_packet_header; +#ifdef __cplusplus +} +#endif + #endif /* OPCODE_TIC6X_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h index 4f0c0d3..5e317da 100644 --- a/include/opcode/v850.h +++ b/include/opcode/v850.h @@ -22,6 +22,10 @@ #ifndef V850_H #define V850_H +#ifdef __cplusplus +extern "C" { +#endif + /* The opcode table is an array of struct v850_opcode. */ struct v850_opcode @@ -237,4 +241,8 @@ extern const struct v850_operand v850_operands[]; extern int v850_msg_is_out_of_range (const char *); +#ifdef __cplusplus +} +#endif + #endif /* V850_H */ |