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authorThiemo Seufer <ths@networkno.de>2006-06-05 16:28:36 +0000
committerThiemo Seufer <ths@networkno.de>2006-06-05 16:28:36 +0000
commita9e24354827513dfb2a1735bafe760ab0825c7ad (patch)
tree47c4b54c3fd84f60dfb164d18d121ac63af41507 /include/opcode
parent2f0122dcdf8897b4eca8be0d228447d123c5d6d4 (diff)
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[ gas/ChangeLog ]
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew appropriate. (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. (mips_ip): Make overflowed/underflowed constant arguments in DSP and MT instructions a fatal error. Use INSERT_OPERAND where appropriate. Improve warnings for break and wait code overflows. Use symbolic constant of OP_MASK_COPZ. (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d, gas/mips/mips32-mt.s: Remove instructions with invalid arguments. * gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file. [ include/opcode/ChangeLog ] * mips.h: Improve description of MT flags.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/mips.h4
2 files changed, 6 insertions, 2 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 6a6f34b..d79816d 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2006-06-05 Thiemo Seufer <ths@mips.com>
+
+ * mips.h: Improve description of MT flags.
+
2006-05-25 Richard Sandiford <richard@codesourcery.com>
* m68k.h (mcf_mask): Define.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index aa8040a..7ff8602 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -353,8 +353,8 @@ struct mips_opcode
"@" 10 bit signed immediate (OP_*_IMM10)
MT ASE usage:
- "!" 1 bit immediate at bit 5
- "$" 1 bit immediate at bit 4
+ "!" 1 bit usermode flag (OP_*_MT_U)
+ "$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)