2013-06-17 Catherine Moore <clm@codesourcery.com>

	    Maciej W. Rozycki  <macro@codesourcery.com>
	    Chao-Ying Fu  <fu@mips.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/eva.d: New.
	* gas/mips/eva.s: New.
	* gas/mips/micromips@eva.d: New.

	gas/
	* config/tc-mips.c (mips_set_options): Add ase_eva.
	(mips_set_options mips_opts): Add ase_eva.
	(file_ase_eva): Declare.
	(ISA_SUPPORTS_EVA_ASE): Define.
	(IS_SEXT_9BIT_NUM): Define.
	(MIPS_CPU_ASE_EVA): Define.
	(is_opcode_valid): Add support for ase_eva.
	(macro_build): Likewise.
	(macro): Likewise.
	(validate_mips_insn): Likewise.
	(validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_EVA and OPTION_NO_EVA.
	(md_longopts): Add -meva and -mno-eva.
	(md_parse_option): Process new options.
	(mips_after_parse_args): Check for valid EVA combinations.
	(s_mipsset): Likewise.

	include/
	* opcode/mips.h (OP_SH_EVAOFFSET): Define.
	(OP_MASK_EVAOFFSET): Define.
	(INSN_ASE_MASK): Delete.
	(ASE_EVA): Define.
	(M_CACHEE_AB, M_CACHEE_OB): New.
	(M_LBE_OB, M_LBE_AB): New.
	(M_LBUE_OB, M_LBUE_AB): New.
	(M_LHE_OB, M_LHE_AB): New.
	(M_LHUE_OB, M_LHUE_AB): New.
	(M_LLE_AB, M_LLE_OB): New.
	(M_LWE_OB, M_LWE_AB): New.
	(M_LWLE_AB, M_LWLE_OB): New.
	(M_LWRE_AB, M_LWRE_OB): New.
	(M_PREFE_AB, M_PREFE_OB): New.
	(M_SCE_AB, M_SCE_OB): New.
	(M_SBE_OB, M_SBE_AB): New.
	(M_SHE_OB, M_SHE_AB): New.
	(M_SWE_OB, M_SWE_AB): New.
	(M_SWLE_AB, M_SWLE_OB): New.
	(M_SWRE_AB, M_SWRE_OB): New.
	(MICROMIPSOP_SH_EVAOFFSET): Define.
	(MICROMIPSOP_MASK_EVAOFFSET): Define.

	opcodes/
	* micromips-opc.c (EVA): Define.
	(TLBINV): Define.
	(micromips_opcodes): Add EVA opcodes.
	* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
	(print_insn_args): Handle EVA offsets.
	(print_insn_micromips): Likewise.
	* mips-opc.c (EVA): Define.
	(TLBINV): Define.
	(mips_builtin_opcodes): Add EVA opcodes.

2 files changed, 77 insertions, 5 deletions

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ecf4b11..4daf47b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,30 @@
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+	    Chao-Ying Fu  <fu@mips.com>
+
+	* mips.h (OP_SH_EVAOFFSET): Define.
+	(OP_MASK_EVAOFFSET): Define.
+	(INSN_ASE_MASK): Delete.
+	(ASE_EVA): Define.
+	(M_CACHEE_AB, M_CACHEE_OB): New.
+	(M_LBE_OB, M_LBE_AB): New.
+	(M_LBUE_OB, M_LBUE_AB): New.
+	(M_LHE_OB, M_LHE_AB): New.
+	(M_LHUE_OB, M_LHUE_AB): New.
+	(M_LLE_AB, M_LLE_OB): New.
+	(M_LWE_OB, M_LWE_AB): New.
+	(M_LWLE_AB, M_LWLE_OB): New.
+	(M_LWRE_AB, M_LWRE_OB): New.
+	(M_PREFE_AB, M_PREFE_OB): New.
+	(M_SCE_AB, M_SCE_OB): New.
+	(M_SBE_OB, M_SBE_AB): New.
+	(M_SHE_OB, M_SHE_AB): New.
+	(M_SWE_OB, M_SWE_AB): New.
+	(M_SWLE_AB, M_SWLE_OB): New.
+	(M_SWRE_AB, M_SWRE_OB): New.
+	(MICROMIPSOP_SH_EVAOFFSET): Define.
+	(MICROMIPSOP_MASK_EVAOFFSET): Define.
+
 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 
 	* nios2.h (OP_MATCH_ERET): Correct eret encoding.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 0bb9c11..9d241e8 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -330,6 +330,10 @@
 #define OP_MASK_IMMY		0
 #define OP_SH_IMMY		0
 
+/* Enhanced VA Scheme */
+#define OP_SH_EVAOFFSET		7
+#define OP_MASK_EVAOFFSET	0x1ff
+
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
@@ -521,6 +525,9 @@ struct mips_opcode
    "+z" 5-bit rz register (OP_*_RZ)
    "+Z" 5-bit fz register (OP_*_FZ)
 
+   Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+
    Other:
    "()" parens surrounding optional value
    ","  separates operands
@@ -537,7 +544,7 @@ struct mips_opcode
    following), for quick reference when adding more:
    "1234"
    "ABCDEFGHIJPQSTXZ"
-   "abcpstxz"
+   "abcjpstxz"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -733,9 +740,6 @@ static const unsigned int mips_isa_table[] =
 #define INSN_OCTEONP		  0x00000200
 #define INSN_OCTEON2		  0x00000100
 
-/* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK		  0x3c00f0d0
-
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
 
@@ -774,6 +778,8 @@ static const unsigned int mips_isa_table[] =
 #define ASE_DSP64		0x00000002
 /* DSP R2 ASE  */
 #define ASE_DSPR2		0x00000004
+/* Enhanced VA Scheme */
+#define ASE_EVA			0x00000008
 /* MCU (MicroController) ASE */
 #define ASE_MCU			0x00000010
 /* MDMX ASE */
@@ -1020,6 +1026,8 @@ enum
   M_BNEL_I,
   M_CACHE_AB,
   M_CACHE_OB,
+  M_CACHEE_AB,
+  M_CACHEE_OB,
   M_DABS,
   M_DADD_I,
   M_DADDU_I,
@@ -1061,8 +1069,12 @@ enum
   M_LA_AB,
   M_LB_A,
   M_LB_AB,
+  M_LBE_OB,
+  M_LBE_AB,
   M_LBU_A,
   M_LBU_AB,
+  M_LBUE_OB,
+  M_LBUE_AB,
   M_LCA_AB,
   M_LD_A,
   M_LD_OB,
@@ -1082,8 +1094,12 @@ enum
   M_LDR_OB,
   M_LH_A,
   M_LH_AB,
+  M_LHE_OB,
+  M_LHE_AB,
   M_LHU_A,
   M_LHU_AB,
+  M_LHUE_OB,
+  M_LHUE_AB,
   M_LI,
   M_LI_D,
   M_LI_DD,
@@ -1093,10 +1109,14 @@ enum
   M_LL_OB,
   M_LLD_AB,
   M_LLD_OB,
+  M_LLE_AB,
+  M_LLE_OB,
   M_LQ_AB,
   M_LS_A,
   M_LW_A,
   M_LW_AB,
+  M_LWE_OB,
+  M_LWE_AB,
   M_LWC0_A,
   M_LWC0_AB,
   M_LWC1_A,
@@ -1109,6 +1129,8 @@ enum
   M_LWL_A,
   M_LWL_AB,
   M_LWL_OB,
+  M_LWLE_AB,
+  M_LWLE_OB,
   M_LWM_AB,
   M_LWM_OB,
   M_LWP_AB,
@@ -1116,6 +1138,8 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWR_OB,
+  M_LWRE_AB,
+  M_LWRE_OB,
   M_LWU_AB,
   M_LWU_OB,
   M_MSGSND,
@@ -1134,6 +1158,8 @@ enum
   M_OR_I,
   M_PREF_AB,
   M_PREF_OB,
+  M_PREFE_AB,
+  M_PREFE_OB,
   M_REM_3,
   M_REM_3I,
   M_REMU_3,
@@ -1158,6 +1184,8 @@ enum
   M_SC_OB,
   M_SCD_AB,
   M_SCD_OB,
+  M_SCE_AB,
+  M_SCE_OB,
   M_SD_A,
   M_SD_OB,
   M_SD_AB,
@@ -1194,11 +1222,17 @@ enum
   M_SNE_I,
   M_SB_A,
   M_SB_AB,
+  M_SBE_OB,
+  M_SBE_AB,
   M_SH_A,
   M_SH_AB,
+  M_SHE_OB,
+  M_SHE_AB,
   M_SQ_AB,
   M_SW_A,
   M_SW_AB,
+  M_SWE_OB,
+  M_SWE_AB,
   M_SWC0_A,
   M_SWC0_AB,
   M_SWC1_A,
@@ -1211,6 +1245,8 @@ enum
   M_SWL_A,
   M_SWL_AB,
   M_SWL_OB,
+  M_SWLE_AB,
+  M_SWLE_OB,
   M_SWM_AB,
   M_SWM_OB,
   M_SWP_AB,
@@ -1218,6 +1254,8 @@ enum
   M_SWR_A,
   M_SWR_AB,
   M_SWR_OB,
+  M_SWRE_AB,
+  M_SWRE_OB,
   M_SUB_I,
   M_SUBU_I,
   M_SUBU_I_2,
@@ -1638,6 +1676,10 @@ extern const int bfd_mips16_num_opcodes;
 #define MICROMIPSOP_SH_FZ		0
 #define MICROMIPSOP_MASK_FZ		0
 
+/* microMIPS Enhanced VA Scheme */
+#define MICROMIPSOP_SH_EVAOFFSET	0
+#define MICROMIPSOP_MASK_EVAOFFSET	0x1ff
+
 /* These are the characters which may appears in the args field of a microMIPS
    instruction.  They appear in the order in which the fields appear
    when the instruction is used.  Commas and parentheses in the args
@@ -1795,6 +1837,9 @@ extern const int bfd_mips16_num_opcodes;
    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
 
+   microMIPS Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+
    Other:
    "()" parens surrounding optional value
    ","  separates operands
@@ -1809,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
-   ""
+   "j"
    ""
    "ABCDEFGHI"
    ""