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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2010-12-18 11:14:14 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2010-12-18 11:14:14 +0000 |
| commit | 986754024085408d77fabdc6e1e94fa2b8221b7f (patch) | |
| tree | 4f6313245d69122a6630ea1137dc24ab934f5e52 /include/opcode | |
| parent | e6a3fb4b5cc97668b0822c98d7896a5fca165360 (diff) | |
| download | gdb-986754024085408d77fabdc6e1e94fa2b8221b7f.zip gdb-986754024085408d77fabdc6e1e94fa2b8221b7f.tar.gz gdb-986754024085408d77fabdc6e1e94fa2b8221b7f.tar.bz2 | |
include/opcode/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
opcodes/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
(mips_builtin_opcodes): Add loongson3a specific instructions.
* mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.
gas/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* config/tc-mips.c (insn_uses_reg): Handle the new flags
INSN2_READ_FPR_Z, INSN2_READ_GPR_D and INSN2_READ_GPR_Z.
(append_insn): Handle delay-slot filling for the new flags.
(validate_mips_insn): Handle the new arguments +a|b|c|z|Z.
(mips_ip): Handle the new arguments +a|b|c|z|Z.
gas/testsuite/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
gas/mips/loongson-3a-3.s, gas/mips/loongson-3a-3.d: New tests.
* gas/mips/mips.exp: Run them.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 23 |
2 files changed, 29 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 85ae8ab..f68805f 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,9 @@ +2010-12-18 Mingjie Xing <mingjie.xing@gmail.com> + + * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) + (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) + (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. + 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Fix previous commit. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f707d46..f6656a6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -226,6 +226,18 @@ #define OP_SH_SEQI 6 #define OP_MASK_SEQI 0x3ff +/* Loongson */ +#define OP_SH_OFFSET_A 6 +#define OP_MASK_OFFSET_A 0xff +#define OP_SH_OFFSET_B 3 +#define OP_MASK_OFFSET_B 0xff +#define OP_SH_OFFSET_C 6 +#define OP_MASK_OFFSET_C 0x1ff +#define OP_SH_RZ 0 +#define OP_MASK_RZ 0x1f +#define OP_SH_FZ 0 +#define OP_MASK_FZ 0x1f + /* This structure holds information for a particular instruction. */ struct mips_opcode @@ -503,6 +515,17 @@ struct mips_opcode only be set for macros. For instructions, FP_D in pinfo carries the same information. */ #define INSN2_M_FP_D 0x00000010 +/* Modifies the general purpose register in OP_*_RZ. */ +#define INSN2_WRITE_GPR_Z 0x00000020 +/* Modifies the floating point register in OP_*_FZ. */ +#define INSN2_WRITE_FPR_Z 0x00000040 +/* Reads the general purpose register in OP_*_RZ. */ +#define INSN2_READ_GPR_Z 0x00000080 +/* Reads the floating point register in OP_*_FZ. */ +#define INSN2_READ_FPR_Z 0x00000100 +/* Reads the general purpose register in OP_*_RD. */ +#define INSN2_READ_GPR_D 0x00000200 + /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that |